Cpre488 wikidb-cpre488 https://wikis.ece.iastate.edu/cpre488/index.php/Main_Page MediaWiki 1.26.3 first-letter Media Special Talk User User talk Cpre488 Cpre488 talk File File talk MediaWiki MediaWiki talk Template Template talk Help Help talk Category Category talk 0 1 272 271 2024-02-09T17:40:33Z Phjones 7 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==VIVADO Tricks and Tips== '''Q: ''' How do I make a signal in my Block Diagram connect to physical pins of the FPGA (e.g., to connect to a VGA connector) '''A: ''' Right-click on the wire you want to connect to a physical pin of the FPGA. Then select the option "Make External". Note: the name of this signal needs to match the name of a corresponding line in your .xdc file. '''<u>Internal Logic Analyzer (ILA) </u>''': '''Q: ''' When trying to open target on VIVADO to look at the ILA, a warning appears saying there are no connected debug cores. How do I fix this issue? '''A: ''' One possible fix is to to compile and run the software in VITIS first. Once you have done this, in VIVADO refresh device or click auto-connect again. It may then be able to then find the debug cores and you can begin using the ILA to debug the hardware. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I try to compile my launcher driver it cannot find launcher_commands.h '''A: ''' To tell petalinux that you want to include launcher_commands.h in the build process you need to modify the driver's .bb file. Within the petalinux project in your launcher-driver folder, open the launcher-driver.bb file. On the SRC_URI line, add a path to launcher_commands.h. If you put this in the files subdirectory with your C file, this line would be <i>file://launcher_commands.h \</i> '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> An alternative summary of Picoscope settings to try: <ul> <li>Mode = Repeat / Auto </li> <li>Type = Interval </li> <li>Time 1 = 5ms </li> <li>Time Condition = Greater Than </li> </ul> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 045c264edf21f0db9e552533fbbf4d4b296e7586 271 270 2024-02-02T00:21:45Z Phjones 7 /* VIVADO Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==VIVADO Tricks and Tips== '''Q: ''' How do I make a signal in my Block Diagram connect to physical pins of the FPGA (e.g., to connect to a VGA connector) '''A: ''' Right-click on the wire you want to connect to a physical pin of the FPGA. Then select the option "Make External". Note: the name of this signal needs to match the name of a corresponding line in your .xdc file. '''<u>Internal Logic Analyzer (ILA) </u>''': '''Q: ''' When trying to open target on VIVADO to look at the ILA, a warning appears saying there are no connected debug cores. How do I fix this issue? '''A: ''' One possible fix is to to compile and run the software in VITIS first. Once you have done this, in VIVADO refresh device or click auto-connect again. It may then be able to then find the debug cores and you can begin using the ILA to debug the hardware. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I try to compile my launcher driver it cannot find launcher_commands.h '''A: ''' To tell petalinux that you want to include launcher_commands.h in the build process you need to modify the driver's .bb file. Within the petalinux project in your launcher-driver folder, open the launcher-driver.bb file. On the SRC_URI line, add a path to launcher_commands.h. If you put this in the files subdirectory with your C file, this line would be <i>file://launcher_commands.h \</i> '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 1965b2bd097d0885891cacddce0937a604333634 270 269 2024-02-02T00:00:52Z Phjones 7 /* VIVADO Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==VIVADO Tricks and Tips== '''<u>Internal Logic Analyzer (ILA) </u>''': '''Q: ''' When trying to open target on VIVADO to look at the ILA, a warning appears saying there are no connected debug cores. How do I fix this issue? '''A: ''' One possible fix is to to compile and run the software in VITIS first. Once you have done this, in VIVADO refresh device or click auto-connect again. It may then be able to then find the debug cores and you can begin using the ILA to debug the hardware. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I try to compile my launcher driver it cannot find launcher_commands.h '''A: ''' To tell petalinux that you want to include launcher_commands.h in the build process you need to modify the driver's .bb file. Within the petalinux project in your launcher-driver folder, open the launcher-driver.bb file. On the SRC_URI line, add a path to launcher_commands.h. If you put this in the files subdirectory with your C file, this line would be <i>file://launcher_commands.h \</i> '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 27d2e461e60f7bece5fd8f7adea623ce5f9bb6ed 269 268 2024-02-01T22:34:39Z Phjones 7 /* VIVADO Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==VIVADO Tricks and Tips== '''<u>Internal Logic Analyzer (ILA) </u>''': Q: When trying to open target on VIVADO to look at the ILA, a warning appears saying there are no connected debug cores. How do I fix this issue? A: One possible fix is to to compile and run the software in VITIS first. Once you have done this, in VIVADO refresh device or click auto-connect again. It may then be able to then find the debug cores and you can begin using the ILA to debug the hardware. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I try to compile my launcher driver it cannot find launcher_commands.h '''A: ''' To tell petalinux that you want to include launcher_commands.h in the build process you need to modify the driver's .bb file. Within the petalinux project in your launcher-driver folder, open the launcher-driver.bb file. On the SRC_URI line, add a path to launcher_commands.h. If you put this in the files subdirectory with your C file, this line would be <i>file://launcher_commands.h \</i> '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] f6334819c5a6429b3d14032c0be15ca4680fddb0 268 267 2024-01-31T17:10:11Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I try to compile my launcher driver it cannot find launcher_commands.h '''A: ''' To tell petalinux that you want to include launcher_commands.h in the build process you need to modify the driver's .bb file. Within the petalinux project in your launcher-driver folder, open the launcher-driver.bb file. On the SRC_URI line, add a path to launcher_commands.h. If you put this in the files subdirectory with your C file, this line would be <i>file://launcher_commands.h \</i> '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] c5b492de178eb38743cc463b32a49816ed448ab3 267 266 2024-01-16T16:52:19Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I try to compile my launcher driver it cannot find launcher_commands.h '''A: ''' To tell petalinux that you want to include launcher_commands.h in the build process you need to modify the driver's .bb file. Within the petalinux project in your launcher-driver folder, open the launcher-driver.bb file. On the SRC_URI line, add a path to launcher_commands.h. If you put this in the files subdirectory with your C file, this line would be <i>file://launcher_commands.h \</i> '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <!-- <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. --> ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ae0a0d44557476203009bebd3b17b03b1f5289d5 266 265 2023-03-24T14:57:25Z Akfrank 32 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I try to compile my launcher driver it cannot find launcher_commands.h '''A: ''' To tell petalinux that you want to include launcher_commands.h in the build process you need to modify the driver's .bb file. Within the petalinux project in your launcher-driver folder, open the launcher-driver.bb file. On the SRC_URI line, add a path to launcher_commands.h. If you put this in the files subdirectory with your C file, this line would be <i>file://launcher_commands.h \</i> '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] c5b492de178eb38743cc463b32a49816ed448ab3 265 264 2023-02-23T23:49:57Z Phjones 7 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 7b00aebfc72842f9b30988c7e3646c7cf1277712 264 263 2023-02-23T23:42:50Z Phjones 7 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] This can also be found in the docs/IP directory of you MP-2.zip you downloaded,=. '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 61c162cfe3334599e6875633dbcbc9fb06bae8b6 263 262 2023-02-01T12:49:45Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] b67a40dca1a97bbcf064230e148e93d9e04815f1 262 261 2023-01-17T17:18:55Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <!-- <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. --> ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 2b4de448178fb7ff0b7d11258b752928598824c2 261 260 2022-03-24T15:16:34Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot to load the Linux root file system to a different location. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 9828618d9e5390197cfae5a3998c5a63a85c54f1 260 259 2022-03-24T15:12:53Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process, the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot where to load the Linux root file system. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.zip] <B> rename from .zip to .scr </B>) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] dd288a7b759c42e84f8e80dbfeb3bb1c97e1bf89 259 258 2022-03-24T15:09:58Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process, the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot where to load the Linux root file system. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/boot.scr]) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] dc2c608c9ff13670a008a6d11a0dec35ea7e64e0 258 257 2022-03-24T15:07:06Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process, the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process Linux is overwriting some of the data space that is being used by the camera hardware. A tell-tale sign of this is if before your camera shuts off you see artifacts displayed to the monitor. This is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with by having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot where to load the Linux root file system. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip]) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file (that has a valid CRC) by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 0598c39681a456f84e0589b501cc30c87e4f31f7 257 256 2022-03-24T15:03:46Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' When I boot Linux with my MP-2 based hardware, the camera starts running as expected, but at some point during the Linux boot up process, the camera abruptly turns off? '''A: ''' There is a good chance that during the boot process, Linux is overwriting so of the data space that was being used by the camera hardware. A tell-tale sign of this is if before you camera shuts off you see odd artifacts display to the monitor, this is basically what part of your Linux rootfs looks like in YCrCb format. This can be dealt with my having U-boot load your Linux kernel starting from a different location. One way of accomplishing this is to provide a boot.scr script to U-boot that tells U-boot where to load the Linux root file system. Here are two way you can do this: * Option 1: Try using this pre-built boot.scr file ([http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip]) instead of the one provided by petalinux. It contains the following commands: <p style="font-family:'Courier New'"> fatload mmc 0 0x15000000 image.ub <BR> bootm 0x15000000 </p> * Option 2: Built your own boot.scr file by preforming the following steps. <ol> <li> Locate the mkimage for targeting the ARM processor </li> Can be found hiding in the petalinux directory structure. Here are a couple places to start checking: * <span style="font-family:'Courier New'"> <project-location>/avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+git999-r0/recipe-sysroot-native/usr/bin/mkimage </span> * <span style="font-family:'Courier New'"> avnet-digilent-zedboard-2020.1/build/tmp/work/zedboard_zynq7-xilinx-linux-gnueabi/linux-xlnx/5.4+gitAUTOINC+22b71b4162-r0/recipe-sysroot-native/usr/bin/mkimage </span> <li> Place the u-boot commands you want to execute into a .txt file, let us call it <B>boot.txt </B> </li> <li> Build a boot.scr file, by running the following command: </li> <p style="font-family:'Courier New'"> <PATH-to-mkimage>/mkimage -A arm -O linux -T script -C none -n "My Boot" -d boot.txt boot.scr </p> </ol> '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core <BR> cd recipes-core <BR> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend <BR> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" <BR> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ae3ecbe5617c27d446fb6b0246e2728a727fc23b 256 255 2022-03-23T22:05:13Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core </p> <p style="font-family:'Courier New'"> cd recipes-core </p> <p style="font-family:'Courier New'"> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend </p> <p style="font-family:'Courier New'"> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" </p> <p style="font-family:'Courier New'"> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' <B>non-Petalinux:</B> I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' <B>non-Petalinux:</B> I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' <B>non-Petalinux:</B> How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' <B>non-Petalinux:</B> What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 8a682696641976612503aaa8920741d8bacc0268 255 254 2022-03-23T22:00:33Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core </p> <p style="font-family:'Courier New'"> cd recipes-core </p> <p style="font-family:'Courier New'"> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend </p> <p style="font-family:'Courier New'"> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" </p> <p style="font-family:'Courier New'"> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] e7c9c32bc01db6c9b1c480908fc3b91598f2ad4b 254 253 2022-03-23T21:59:58Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core </p> <p style="font-family:'Courier New'"> cd recipes-core </p> <p style="font-family:'Courier New'"> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend </p> <p style="font-family:'Courier New'"> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" </p> <p style="font-family:'Courier New'"> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? '''A: ''' Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 5d2f95650bc4998a64f2c553d09a7a3d5f643f7c 253 252 2022-03-23T21:59:01Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core </p> <p style="font-family:'Courier New'"> cd recipes-core </p> <p style="font-family:'Courier New'"> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend </p> <p style="font-family:'Courier New'"> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" </p> <p style="font-family:'Courier New'"> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 3059751c0e6341422d88c1a9c4b28560717fcb72 252 251 2022-03-23T21:58:15Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The following may help reduce the size: <ul> <li> Remove any video buffers that you may have allocated for your MP2 software project. </li> <li> Comment out libraries that may not be absolutely necessary (e.g., xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h) from your camera.h. This will exclude these libraries from being built with your FSBL. </li> <li> Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera code by itself to make sure your changes are correct. </li> </ul> Attempt to rebuild the fsbl project. The size of the code compiled needs to be less, than about 250KB. If it is still to big, try changing the build optimization setting to compile for size (-Os) '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core </p> <p style="font-family:'Courier New'"> cd recipes-core </p> <p style="font-family:'Courier New'"> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend </p> <p style="font-family:'Courier New'"> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" </p> <p style="font-family:'Courier New'"> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] e3eba0bbcead594d4e4c6c5c4947eee8cb98dafa 251 250 2022-03-23T21:45:49Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core </p> <p style="font-family:'Courier New'"> cd recipes-core </p> <p style="font-family:'Courier New'"> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend </p> <p style="font-family:'Courier New'"> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" </p> <p style="font-family:'Courier New'"> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 3deebc832e404da742b7065bd3ba4d43fbff8517 250 249 2022-03-23T21:45:10Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' The flowing step show you how to check if RX is installed, and if not how to configure the Linux rootfs to enable RX. <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: </li> <p style="font-family:'Courier New'">busybox --list options </p> If RX is not found, then in Petalinux RX needs to be enabled, built, and packaged into the rootfs. <li> Go to: <span style="font-family:'Courier New'"> <project-root>/meta-user </span> </li> <li> Create the following sub-direcoty <span style="font-family:'Courier New'"> recipes-core/busybox </span>: </li> <p style="font-family:'Courier New'"> mkdir recipes-core </p> <p style="font-family:'Courier New'"> cd recipes-core </p> <p style="font-family:'Courier New'"> mkdir busybox </p> <li> Inside of the busybox subdirectory create a file called "busybox_1%.bbappend", and a subdirectory called "files": </li> <p style="font-family:'Courier New'"> touch busybox_1%.bbappend </p> <p style="font-family:'Courier New'"> mkdir files </p> <li> Inside of the <B>"files"</B> directory create a file called <B>"user.cfg"</B>: </li> <p style="font-family:'Courier New'"> touch user.cfg </p> <li> Open the file <B>"user.cfg"</B>, and add the following line. Note: The label for the config option to turn on was found in <span style="font-family:'Courier New'"> <project-root>/components/yocto/layers/core/meta-poky/recipes-core/busybox/busybox/poky-tiny/defconfig </span>: </li> <p style="font-family:'Courier New'"> CONFIG_RX=y </p> <li> Open the file <B>"busybox_1%.bbappend" </B>, and add the following lines: </li> <p style="font-family:'Courier New'"> FILESEXTRAPATHS_prepend := "${THISDIR}/files:" </p> <p style="font-family:'Courier New'"> SRC_URI += "file://user.cfg" </p> <li> Build busybox: </li> <p style="font-family:'Courier New'"> petalinux-build -c busybox </p> <li> Copy the updated <B>"image.ub"</B> to your SD card: </li> <li> Boot Linux from the SD card. Once you have logged run the following command, it should show RX as one of the options: </li> <p style="font-family:'Courier New'"> busybox --list options </p> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 32f771901ef3f274f85effc29e3e1231e1355401 249 248 2022-03-23T21:05:22Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! Note: If RX is not installed/configured for you Linux, see the FAQ on how to configure Linux to enable it. '''Q: ''' RX does not appear to exist in Linux configuration that I am running on the Zedboad. How can I enable it. '''A: ''' <ol> <li> List supported Busybox applets while running Linux on the ZedboardCheck to check if RX has been enabled for busybox: busybox --list options </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] affe658ff82242e5b5a72d5cfc074b537d04188a 248 247 2022-03-18T23:03:41Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: [http://class.ece.iastate.edu/cpre488/resources/wiki/putty.zip] Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 5d776e4baf97768f1252f3e2f745f0ff88944b9d 247 246 2022-03-18T22:59:11Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: * Original Link:[http://www.extraputty.com/snapshots/Download/thanksputty.html link]. * Local Link: Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ae034388868cec2b52215fe0da02853215b969ce 246 245 2022-03-11T00:44:05Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How do I share a folder between by Virtualbox Linux, and Windows? Here are several options for sharing data between you Virtualbox guest OS, and host OS: *Creating a shared folder: https://www.youtube.com/watch?v=FYmck1G0fqY *Setting permission in Ubuntu to access the shared folder: https://www.youtube.com/watch?v=u2Ha0peg9V4 *A few other options: https://pureinfotech.com/create-shared-folder-virtual-machine-virtualbox/ '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] cccc894d350eda81e914f2f142c18991964bb099 245 244 2022-02-24T20:40:59Z Phjones 7 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example Clean logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] c1e9383456a14d352dd6791689c32e1f3c04830a 244 243 2022-02-24T20:39:43Z Phjones 7 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/error-log-example.txt] Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/wiki/pretty-clean-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 4b1bc0b63e89cbb3a6a967ee27292520e42484c7 243 242 2022-02-24T20:38:33Z Phjones 7 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/error-log-example.txt] Example error logfile: [http://class.ece.iastate.edu/cpre488/resources/error-log-example.txt] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ebf230f77373f110a6516fc1dd8cfc187462fefb 242 241 2022-02-24T20:27:32Z Phjones 7 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ce29aa3a706b5c8d5bc7133c68a891dcb967e3a0 241 240 2022-02-24T20:26:08Z Phjones 7 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 3094f28d9fd68dbc8277ed7ebfbc9180eb4b4ffe 240 239 2022-02-24T20:24:04Z Phjones 7 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' Regenerating HDL Wrapper - After adding/removing components to/from our Block Diagram or adding/removing an externally connected signal/port, we start see weird warnings/errors during synthesis (e.g., "Port 'signal name' is missing in component declaration", "tying undriven pin clk to constant 0") '''A: ''' Some teams may have run into this issue in MP0, and/or some in MP1, when you add a component to your block diagram (or make a signal an External Port) your top level HDL wrapper does not update. When you start getting odd errors in VIVADO it is always a good idea to examine your HDL wrapper to make sure it looks reasonable. If it does not, then remove and regenerate it. Generally speaking, when trying to debug issues with the Xilinx Tools, the log files are your friend. They tend to give much more detail than the console summary messages. I have saved and attached two logfiles. One logfile with the warnings/errors that some teams have seen after adding components, and one that is a somewhat clean logfile after deleting and regenerated the HDL wrapper. You will notice near the beginning of the error log file a ton of warnings of the form: "Port 'signal name' is missing in component declaration" This is a pretty huge red flag that something is amiss, and one of the first places to check is if your xdc file, and HDL wrapper are matching. If you were to open your HDL wrapper file, you should see that indeed many of the ports for those new IP cores are not there. By deleting the HDL wrapper, and regenerating you should see those ports in the newly generated HDL wrapper. Since many of the ports of your IP block that were to be external where not recognized by the HDL wrapper, the tool just tied them to constants. Then later the tool for example noticed things like clocks being tied to a constant values, thus threw errors. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ee264bf7bf531a6245578c51eb744367382af095 239 238 2022-02-11T16:05:30Z Phjones 7 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: <ol> <li> Set the trigger to repeat or auto </li> <li> Click the square wave looking button next to the trigger selection </li> <li> Select pulse wave from the left hand menu </li> <li> Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) </li> <li> Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted)</li> </ol> This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 0efb51ba03487819f23c4d50de7257dfe54343d6 238 237 2022-02-11T16:00:55Z Phjones 7 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' When using the picoscope to anaylze the RC controller's PPM signal, I can't seem to get the PPM to stay in one place? '''A: ''' Here are some simple picoscope adjustments to make while observing the PPM waveforms: 1. Set the trigger to repeat or auto 2. Click the square wave looking button next to the trigger selection 3. Select pulse wave from the left hand menu 4. Adjust the time setting (a vale from 8ms-20ms has typically worked well for the RC's PPM) 5. Adjust the window zoom, make sure that the view is not scrolled past the signal (using the scroll wheel to get an appropriate window size seems to work well) (in the zoom selection window, the size and position of the zoom selection can be adjusted) This can all be done while running to make sure what you want to observe is in the window. '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 62f406b6c67c75709866ab06c00adf8787b4a848 237 236 2022-02-05T21:51:07Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, and clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check out the diagram on page 6. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] a57912e85fabb1bb99d4a938daf853438dc3a6db 236 235 2022-02-05T21:46:37Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black (and perhaps the last column). '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 872bf7028b036cf50f7371761f0c36461e65419d 235 234 2022-02-05T20:11:58Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here is how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 9987b08a3a9419ab472da79510a36a64de8a462e 234 233 2022-02-04T21:30:05Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] caf9d50ae9a5e901ab54222049d9ba5cf3211dba 233 232 2022-01-26T19:16:45Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTY are showing that the code is getting stuck during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <!-- <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. --> ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] e3e6a892e1ae6fff5d6e402c22f59c2218774efd 232 231 2022-01-26T19:14:11Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <!-- <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. --> ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 95cc01c126f4c62ab5794d5354efc20fc147fe0a 231 230 2021-04-02T16:05:52Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Go to the top-level Linux source directory, and then run these commands. *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] d0e2c7520a1d3ce6423cb53a8e7bf8dca2f8e660 230 229 2021-04-02T15:47:59Z Phjones 7 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' I keep forgetting the commands for setting up the cross-compiler environment '''A: ''' Setting up cross compiler environment needs to be run inside of each new Linux terminal you open. Here are the commands to run Setting up cross compiler environment. Needs to be run inside of each new Linux terminal you open: *source /remote/Xilinx/2018.3/SDK/2018.3/settings64.sh *export CROSS_COMPILE=arm-linux-gnueabihf- *export ARCH=arm '''Q: ''' I have downloaded the Linux Kernel OS source code, how do I compile it? '''A: ''' Here are the commands to rum *Go into top-level Linux source directory *make ARCH=arm xilinx_zynq_defconfig *make ARCH=arm menuconfig *Under “Device Drivers -> USB support”, select the “Announce new device” option. *make ARCH=arm UIMAGE_LOADADDR=0x8000 uImage -j 24 (Note the 24 should be the number of processing cores your machine has) '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 7f34205f4e7eaa60d81103b2eea9954a6afcb25c 229 228 2021-02-17T20:41:05Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. There are a number of ways you can resolved this mismatch from occurring. The following is the cleanest method I have found: <ol> <li> Add your GPIO IP block, </li> <li> Make the output External, </li> <li> Give this output a name, </li> <li> Save your block diagram, </li> <li> Click the option to create an HDL Wrapper. This will make/update the wrapper to include this newly added external pin, </li> <li> Open the HDL wrapper file that was created/updated, </li> <li> Check the name the wrapper gives the external pin. You should see that it has appended _tir_i to the pin name that you gave, </li> <li> Use the name that the wrapper gives in your .xdc file. </li> </ol> * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 8ca3f6fd04fa39e45a26b3b8542d06d802609e95 228 227 2021-02-17T20:04:12Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. Keeping this error from occurring in the first place is a little tricky, if you end the name of your GPIO external pin with "_tri_i", and update you .xcd file to match. The tools should be happy. But I have seen the tools just add another _tri_i, giving you a name in the VHDL wrapper file ending _tri_i_tri_i. My recommendation is to not have the _tri_i in the Block Diagram, but append it to signal name in the .xdc file, and manually modify the name in all places it appears in your VHDL wrapper file to end in _tri_i. * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 204dd8925915f93ab8921d32ed05202a475a4e27 227 226 2021-02-17T20:01:22Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. Keeping this error from occurring in the first place is a little tricky, if you end the name of your GPIO external pin with "_tri_i", and update you .xcd file to match. The tools should be happy. But I have seen the tools just add another _tri_i, giving you a name in the VHDL wrapper file making it end with _tri_i_tri_i. My recommendation is to not have the _tri_i in the Block Diagram, but append it to signal name in the .xdc file, and manually modify the name in all places it appears in your VHDL wrapper file to end in _tri_i. * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 5b4c0a84ce4a09a571458ff31610af566b6bfeb6 226 225 2021-02-17T18:14:01Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When I tried to connect the virtual switches / buttons using PMOD C, and PMOD D, I am getting weird errors bout "tri" signals. Where did this come from? '''A: ''' The tools are trying to be "smart"/"helpful", and are noticing that the GPIO IP block has the ability to be a tri-state interface. In response to this, during the bitfile generation (or synthesis) process it updates your VHDL wrapper file to append "_tri_i" to the end of the name you gave the external pin in your Block Diagram. This causes the VHDL wrapper name not to match the name you gave in your .xdc file. To avoid this, if you make sure to end the name of your GPIO external pin with "_tri_i", and update you .xcd file to match. The tools should be happy. * One may ask: Why did the physical buttons and switches not give this issue? You will notice that for the physical buttons / switches / leds you did not have to add these to your .xdc file. This is because they are known by the Zedboard settings, thus takes care of this details behind the scene . You can see this if you open your VHDL wrapper file, you will notice that the physical buttons / switches / leds, have had "_tri_i" or "_tri_o" appended to the name shown in the block diagram's external pin name. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 07c3042c5afb8c651f2dd14bb7189eecd948e662 225 224 2021-02-15T18:58:09Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] bb55c638d594718548f352fc766781eaa983aa0b 224 221 2021-02-15T18:57:10Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your NES lscript: [[File:lscript-NES.jpg|none|border|thumb|NES setting: Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:lscript-orignal.jpg|none|border|thumb|Hello settings: Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] d93ceeabe82d37a88e33b4105544568f7e81fb4e 221 220 2021-02-15T18:52:12Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' OK. I have the NES code happily compiling, and I think I have made the needed updates to load the default game, and have its start up screen (sequence) display. But the debug print statements we see using PuTTYare showing that the code is getting during the "Boot/Load" stages. What are some things I can do to get past this issue? '''A: ''' There are a couple things going on that need to be taken care of, and both involve updating the loader script (i.e. lscript.ld) of your project. <ol> <li> The "Stack" and "Heap" size that was set by initial "Hello" application is too small. You will need to increase both of these. </li> <li> A trickier issue is noticing that this application does some fixed location static memory allocation. Take a look near the bottom of mmap.h. You will notice a comment indicating that it is performing static memory allocation. Which is fine, but the part we need to deal with using the lscript is that fixed locations are specified. We will deal with this by adding an offset to what we tell the build tool is the base address of DDR memory. This ensures the build tools will not try allocate memory were we have already manually allocated. Basically we are tricking the tool to thing DDR memory starts at a higher address in memory. You can figure out what address to give this script by printing out the value of "WAV_BASEADDR" (e.g. xil_printf("WAV_BASEADDR = %X \r\n", WAV_BASEADDR);). You will notice the value shown in the screen shot is a bit larger that the value printed. This was done to make the math easier for for ensuring that "Base Address" + "Size" adds so that the end of the DDR memory does not change. </li> </ol> The values show in this screen shot should be fine to use in your lscript: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] Here are the values the the "Hello" application originally specified: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] b6650a96a220ff47ccb779585028c0606ca0a376 220 219 2021-02-15T18:12:32Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> <li> Click "Apply and Close" </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 3a741a9a7df239aeae0658bd9181b5380fc21750 219 216 2021-02-15T17:22:41Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": [[File:Include-workspace-folder.jpg|border|caption]] Here is an image of what the include tab should look like after you have added these folders to the Include path: [[File:Add-source-files.jpg|none|border|thumb|Click to Enlarge]] <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 7ba65666e0ea310ee2a3df50d56db551d8d4c315 216 215 2021-02-15T17:06:55Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' I am trying to compile the NES code, and it is giving a TON of compiler errors! Any pointers for how to address these errors? '''A: ''' Yes this will be the case right after you copy the code into your project. This is due to two key things: <ol> <li> Since the code base added subdiretories for source and include files, you need to let the build system know where to look for these files. Here how to do this: </li> <ol type = "a"> <li> Right click on your application project, and select properties</li> <li> Click to expand "C/C++ General" </li> <li> Select "Path and Symbols", then click the "Includes" tab</li> <li> Click "Add..." to add 3 folders to your Include directories: src, NESCore, src/xilsd </li> </ol> Here is an image of what it looks like after you click "Add..." and select to added "xilsd": Here is an image of what the include tab should look like after you have added these folders to the Include path: <li> You will notice in the "mapper" folder there are many .c files throwing errors. These .c files are used in an unconventional manner, and need to be ignored by the build system. You can mark this folder to be ignored as follows </li> <ol type = "a"> <li> Right click on the "mapper" folder </li> <li> Select "Properties" </li> <li> Click on "C/C++ Build" </li> <li> Check "Exclude resource from build", then click "Apply and Close"</li> </ol> The "mapper" folder should now have a grey slash through it, and the name "mapper" should be greyed out. </ol> '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] c154de5eabbc0f85248fb26506e2d737e874de27 215 214 2021-02-12T19:27:30Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you do not have any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 0c2bf191932d2c3f2b0e76963f39cceec355f99e 214 213 2021-02-12T19:25:49Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' What is this ERROR message about: "set_property expects at least one object" '''A: ''' The set_property expects that there exists one thing for it to operate on. A common place this error has occurred for students is when you add the master .xdc file to your project. The following line: set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; is wanting to act upon FPGA pins that are in Bank 13. If you have not any signals connect to the Zedboard PMODs to monitor signals for debugging or using the Virtual Zedboard interface (which uses PMOD C and D), then you will want to comment out this line from the .xcd. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 9a88dfc084cf182a2dc55d8b31ea7f145767c3a5 213 212 2021-02-12T18:53:15Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. <span style="color:#0000FF">'''Q: '''I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? </span> <span style="color:#0000FF">'''A: ''' MP-0: Recommended Approach, Mindset, and Rules of Thumb </span> Class, As you work on MP-0, you will (or have) found that Part 6 is much more challenging than parts 1-5. For Part 6, you are required to form a clear picture of how data is moving through the system and implement that system based on 1) the high-level objective of Part 6, and 2) the documentation of the IP cores needed to complete this part of MP-0 (i.e. VTC, Video Out, and VDMA). <u>'''Recommended approach:'''</u> Some of these steps will be done in parallel. <u>'''A) Draw out the system: '''</u> Get out sheets of paper and a pencil (or better have an MP notebook for this class). As you read through the IP core documentation, sketch how these components connect together. First at a high-level, and then at lower-levels as you learn more details about each IP core. <u>'''B) Understand the technology you are dealing with (write notes about your understanding):'''</u> 1) What does each IP cores do? 2) What is the purpose of each of IP core in the system you are creating? 3) How does each IP core go about doing its job? 4) Make notes on which parts of the Datasheets are appearing to be helpful to your understanding. '''5) Recommendation:''' a) <u>'''In general'''</u>, make a quick 20 minute scan through each datasheet doing the following: i) read introduction/overview pages of each datasheet, ii) scan the whole document to get a sense of the type of architecture and time diagrams present, iii) if there are configuration registers scan them to see their nature, and iv) check if there are usage scenarios described. b) <u>''' Specifically for part 6 of MP-0: '''</u> i) <u>'''Video Out: '''</u> A good starting place, as chapter 1 gives a nice short overview of how this component fits with others, and chapter 2 gives good details on the interfaces that connect Video Out to other IP. ii) <u>''' VTC: '''</u> Chapter 1 gives a nice short overview, and Chapter 2 gives nice descriptions of the interface signals and registers. iii) <u>''' VDMA: '''</u> This core is the most feature-rich of these 3 IP cores. Chapter 1 gives a quick overview, and Chapter 2 gives very useful timing diagrams, among other details (register descriptions, etc.). You will find yourself coming back to Chapter 2 often. ug934_axi_videoIP Chapter 1 is also useful for learning about the AXI-Stream protocol/interface. <u>'''C) Don’t get paralyzed by not knowing everything: '''</u> Datasheets can be loaded with MUCH detail, and parts may be written in a manner for which it is difficult to know with certainty if you are interpreting some aspects correctly or misunderstanding. For your sanity sake, keep in mind those writing these datasheets often may only be a few years ahead of you in terms of work experience. <u>''' 1)Move forward: '''</u> For MP-0, I would recommend spending about <u>'''2 hours'''</u> reading through each of the datasheets for the primary IP cores (VDMA, VTC, Video Out). '''This does <u>not</u> mean reading each IP core datasheet sequentially.''' You will need to skip between them to help build your overall view of the system, and to build your understanding of how they should work together to complete the task at hand (i.e. get an image frame stored in DRAM to display on a monitor). So I would allocate on the order of <u>'''6 hours'''</u> total for this process, before going to 2). <u>''' 2) Build the system: '''</u> Once you have spent time doing parts A, B, and C.1, then build the system as a VIVADO Block Diagram, use VIVADO to build a hardware configuration file, and program the FPGA. You will find there are a number of configuration options for the IP Blocks that you do not understand. <u>'''Make your best guess using the information and level of understanding you have. '''</u> <u>'''3) Don’t get stuck on Error messages given by the tools: '''</u> The VIVADO tool chain is very powerful, and there is a large learning curve to use it like a pro. This is where your TAs (i.e. me) and the Discord discussion form come in. Here is a rule of thumb: Do not spend more than <u>'''30-45 minutes</u>''' struggling own your own to fix VIVADO error messages before posting to or checking Discord (or class wiki) Note: You will want to spend at least <u>'''20 minutes '''</u> struggling and poking around the tools. This is the best way to get use to the tools <u>'''D) Extract evidence from the system: '''</u> The first time you configure the FPGA with your hardware design, and run your software on it (test_vga.c), the most likely outcome is you will be staring at a blank screen! Yes, this can be depressing. And anyone entering the field of embedded systems design has to get use to this initial feeling, and learn how to push through it. Here are actions you can take to work your way from a blank screen to working system: <u>'''1) Software side: '''</u> a) Add print statements to see at point in the SW the system may be getting locked up. b) Add print statements to read the status of registers available for a given IP core. This could give insight into where things are going wrong (either for SW or HW). <u>''' 2) Hardware side: '''</u>OK, you have just downloaded your hardware to the FPGA, ran your software on the hardware, and now you are staring at a blank screen. Is the FPGA completely dead? Is the hardware doing anything? Let’s find out: '''a) Search for life:''' Modify your hardware design to connect “important” signals of your design to ports of the Zedboad (PMOD ports). For example, various clock signals. If you probe a clock signal with an oscilloscope and you get a constant value, then look into why that may be the case (e.g. maybe you have a reset tied to a constant 0, when it is an active-low reset). '''b) Search for intelligent life:''' Check the data sheets for timing-diagrams, and connect some of these related signals to a Zedboad PMOD to see if they are behaving as expected. If not, then dive into the datasheets to find out why, or for hints on what other evidence you can extract from the system to help you isolate the problem. <u>''' E) Work with your TAs/me:'''</u> Once you have spent time extracting evidence from your system. Ping your TAs/me (over Discord) to share what you are seeing, and your theories for why this may be occurring. TAs/me will be able to help you think about what you are seeing, and help suggest next steps you can take to track down what is going wrong with your system. <u>'''F) Stay hopeful:'''</u> Be prepared to not get the results you expect, when trying something. Each time you test a hypothesis, you get one step closer to an operational system. Always keep in mind a list of next step options for forming a clearer picture of what the system is doing, and for discovering why it is behaving in that manner. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] b4902f701dea5b113b96ea9ef077f9acf90b9bd4 212 211 2021-02-12T16:30:32Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. '''Q: ''' I am feeling lost with how to get my VDMA, VTC, VID_OUT hardware design to do anything. Do you have any suggestions for how to move forward? '''A: ''' ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] cf02d2763da43f7e40787ddb73a072697c1fa553 211 210 2021-02-11T17:03:57Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, and tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 8194da1585475c54474157b6c7c6ed52f0aedbbc 210 209 2021-02-11T16:56:53Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to the Integrated Logic Analyzer (ILA) (or you could use available PMOD ports) so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, VIVADO may hide some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in VIVADO or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx VIVADO/VITIS features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 6500e1e561dd616c54ee77b84009e3b5402a8fb8 209 208 2021-02-11T16:52:15Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. * Note: If this does not sync your VITIS software up with the hardware changes you made in VIVADO, you can always just make a new Application project, tell it to use the .xsa that you exported from VIVADO, and copy your C files over to the that new Application project. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 9fc931b8b7a4e649dcd6309550fe40b453d886ea 208 207 2021-02-11T16:48:12Z Phjones 7 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' After making an update to my Hardware in VIVADO, my VITIS software project is not seeing these changes? '''A: ''' Anytime you make an update to your hardware in VIVADO and export an updated .xsa file, you need to make VITIS aware of this. This link explains how to update your VITIS platform project using the Update Hardware Specification option to point the VITIS platform project to the updated .xsa file [https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/ssi1556172680620.html] . Remember to rebuild your Application project. '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] d8d5cd4262eb4ed62066089b21da2a77de48338a 207 206 2020-05-08T15:13:51Z Tdempsay 30 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. '''Q: ''' When I added the camera libraries to the FSBL, it fails to compile. '''A: ''' Depending on your hardware setup and usage of BSP libraries, the compiled elf may be over the maximum size for a FSBL executable. The steps below should help reduce the size. 1. Remove any video buffer used for the last MP software project. 2. Comment out the xrgb2ycrcb.h, xv_demosaic.h, xtpg_app.h, and xvprocess.h from your camera.h. This will exclude these libraries from being built with your FSBL. 3. Try to build. You will likely have errors complaining about missing sources. Which it is! Most of these errors will be with your custom pipeline init stuff (ipipe()). Replace all references to these libraries with hard coded values/addresses. It may be beneficial to run your modified camera stuff by itself to make sure your changes are correct. 4. To make sure it is excluded, right click xtpg_app.c (if you still have it in your project). Resource Configurations -> Exclude From Build, check both boxes. This will explicitly leave the file out when compiling the project. Attempt to rebuild the fsbl project. The reduced size should be around 160kb. If it is still to big, try changing the build optimization setting to compile for size (-Os) A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] fb1f43da4127bb12b88dd50457f103714fbdbde7 206 205 2020-04-01T14:39:03Z Tdempsay 30 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). '''Q: ''' When I plug in the launcher, there are no debug messages that appear from Linux. '''A: ''' Double check that you have the usb debug messages flag set in the kernel config. Make sure the JP2 jumper on the Zedboard is shorted as well, this enables the 5V power connection for the USB port. A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 2133a731167d4bc8d578f52e942ccffd5e100b07 205 204 2020-03-23T23:54:43Z Jtalbert 26 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Use Remote Desktop to remote to any of the remote linux machines ([http://it.eng.iastate.edu/remote/ ISU Remote Access Servers]) * Run the following in bash: source /remote/Xilnx/2018.3/Vivado/2018.3/settings64.sh 'vivado &' or 'xsdk &' '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] b7db7be9c9e57e7e926a347674c569a6546ed9a9 204 203 2020-03-20T18:57:32Z Irex 31 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Include the O_SYNC flag when opening the file to force it to fetch the values on every read and write (which may make accesses slower). A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] f17197901edb8f6b1d7cb7040244d635a1c3af04 203 202 2020-03-20T18:47:55Z Irex 31 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Open the file with the O_SYNC flag to force it to fetch the values on every read and write (which may make accesses slower). A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 7960e5beedf647256333e013f2bdcd659d25ddfd 202 201 2020-03-20T18:47:32Z Irex 31 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". '''Q: ''' When I try to read a pixel value from the memory mapped address ('''mmap(2)'''), the value stays constant. '''A: ''' This means Linux is caching the values from the memory location instead of re-reading them on every access. Open the file with the O_SYNC flag to force it to fetch the values on every read and write (which may make accesses slower). A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] b5890bfc6fd896fadfe68a4189daec83ff8d9ce8 201 200 2020-02-28T16:23:27Z Tdempsay 30 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' How do I get my changes to my axi_ppm IP core to be reflected in Vivado? '''A: ''' After packaging the IP, go back to the MP Vivado project and select Reports>Report IP Status. Your axi_ppm should report itself as obsolete and have an option to upgrade. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 24578701a67ae8fb347ea75bd0a1abf5aa539a4e 200 199 2018-04-04T16:20:54Z Wernsman 28 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} Note: Quad 2 is currently the one on the stand in the back of the lab. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 6eddbf910752eebf647b007c464c92be0e5fcf69 199 198 2018-04-04T16:07:02Z Wernsman 28 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} The address of the quad on the stand is <tt>81:eb:b6:86:e1:d4</tt> ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] d4fa645fe917d98d2b1bee1b24049d60036f15aa 198 197 2018-03-09T17:59:58Z Dhanwada 29 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' When trying to boot from the SD card, my output from PuTTY mentions something about xillydemo.bit and fails to load. '''A: ''' This is likely due to the misconfigured environment variables on the zedboard. After the failure message shows, you will also get an interactive terminal for the board. In this terminal, you can reset the environment variables with the command "env default -a" and save them to the boards memory with the command "saveenv". Power Cycling the board should allow the correct boot file to run. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 6b609940ce10885232a4215e9017e3e6f44683ca 197 196 2018-03-07T16:46:57Z Wernsman 28 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 051e0ae4a4bb263da82b909fc7b5102d1176038f 196 194 2018-03-07T16:46:33Z Wernsman 28 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' What if I encounter an error when trying to convert the device tree to a binary file? '''A: ''' Check that the xilinx.dts file does not contain any duplicate entries and try again. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] a352a151777504da0e5766fbec97e1cd1ffdc38a 194 192 2017-10-13T22:14:49Z Jiztom 25 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 7fe2e72eda56f64e927060317b4054491d4b0640 192 183 2017-10-13T21:37:01Z Jiztom 25 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] '''Remote Access''':<BR/> [https://wikis.ece.iastate.edu/cpre488/index.php/Remote_access Remote Access Tutorial] has been added to access the Zedboard remotely. 50f1521aaa9d4a49030bb4ff1f24eab737a4838e 183 180 2017-03-10T23:13:11Z Imciner2 12 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! '''Q: ''' I get an error saying '''line 1: syntax error: unexpected "("''' when I run my code on a Zedboard. '''A: ''' This means that the file you compiled to run on the Zedboard was not built for the ARM architecture, probably because the cross-compilation environment was not setup. Run the setup.sh script from MP-3 to set it up, and try making the code again. To verify it built correctly, you can use "file [filename]" command on a linux server (not the Zedboard) and it should give you an output that says "[filename]: ELF 32-bit LSB Executable, ARM, Version 1". A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 7fe2e72eda56f64e927060317b4054491d4b0640 180 179 2017-02-22T15:22:37Z Imciner2 12 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! A list of required packages for compiling the Linux kernel on an ECpE remote machine can be found here: [[Packages]]. This list was compiled by running through the lab on a new RHEL7 machine. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 4079e9fd3504ea916f81fb7de240c36393c6a2f3 179 178 2017-01-24T03:56:50Z Imciner2 12 /* XPS Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''I don't see a drop-down menu to connect ports together'''. When XPS runs on Windows 10, this seems to be a recurring issue. There are 2 possible solutions that might help: # Expand the XPS window to cover both monitor screens # Add the "Nets" column to the Ports tab (right-click on the headers). Then the drop-down menu will appear if you click on the Nets column. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 52a4f22af54eea791e92e555f1d0f805495f1eb1 178 177 2017-01-20T16:24:15Z Imciner2 12 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks, Tips, and Common Errors== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ecfdce963f3252357d963f5f94ea706e77cf8dd8 177 176 2017-01-20T16:17:10Z Imciner2 12 /* XPS Tricks, Tips, and Common Errors */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks, Tips, and Common Errors== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"''' or '''No Target with ID 64 in the System'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 29b9da9e2f683cfbc995d3424f5b15e9918e39c8 176 175 2017-01-20T16:14:18Z Imciner2 12 /* XPS Tricks, Tips, and Common Errors */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks, Tips, and Common Errors== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working '''Invalid Command Name: "ps7_init"'''. This error occurs when moving an XSDK workspace from one directory to another (such as moving between people's accounts). The root cause is the program launcher cannot find a file it needs to start the processor cores, so it errors. Luckily the fix is very simple: # Click Run -> Run Configurations # Select the configuration you are using (usually ''project_name''.elf under the Xilinx C/C++ application heading) from the list on the Left # Under the Device Initialization tab, modify the field labeled "Path to initialization TCL file" to have the new path to your workspace # Run the program, and it should now work ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 0cbfed95c6208e2fd389ee41bd08e84f4bb655f3 175 174 2017-01-20T15:58:50Z Imciner2 12 /* XPS Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks, Tips, and Common Errors== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] baeae8403b519dedfaeacc90c700dcc27b60146b 174 173 2017-01-20T15:58:16Z Imciner2 12 /* XPS Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function '''Fatal error: No Input Files'''. This error can occur on Windows when XSDK can't get to the file system path where your source files are located. The root cause of this issue is using UNC paths (aka. \\my.files.iastate.edu\users...) to store and access the project. XSDK requires that a drive letter be used to access the project instead of UNC path. To fix this error do the following: # File -> Switch Workspace -> Other # Click Browse # Expand the U: drive letter (under My PC) # Navigate to the folder the workspace was located in. There is a folder for the Desktop, Documents folder, etc. there that contains the same files as your Windows profile folder # Click Ok, the path displayed should now start with "U:\" # Click Ok, XSDK should now restart and be at the proper directory # Re-compile the code and continue working ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] d7dae712db6b59e75bcd8bfc61c595f2b35f753e 173 162 2017-01-20T15:40:24Z Imciner2 12 /* XPS Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. '''No Active System Dialog Box'''. This dialog opens occasionally in XSDK if you rebuild the program while one was already running. Unfortunately, this confuses XSDK to the point where it needs to be restarted. To fix this error do the following: # Close XSDK, turn off the Zedboard # Re-open XSDK and open the workspace with your project # Turn on the Zedboard, reprogram it with the FPGA file and your softwae # Continue the lab To avoid this problem from happening, always stop the program running on the Zedboard before you build a new version of the software (yes, this gets annoying). There are 2 ways to stop the program: * Press the Red square on the right-side of the console's task bar * Make a switch/button able to end the main while loop and return from the main function ''' ''' ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 98123d7dad7b29a0d30b7796ccfa894868ff8018 162 161 2015-11-06T20:30:47Z Imciner2 12 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:eb:ad:e7:a8:ce</tt> |- |5 |<tt>81:e9:9f:00:f1:a3</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 161 160 2015-11-03T16:36:19Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 160 159 2015-11-03T16:35:51Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 159 158 2015-11-03T16:35:36Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 158 157 2015-09-02T20:50:53Z Imciner2 12 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] '''Q: ''' I type ''xsdk &'' or ''xps &'' in the terminal and nothing is appearing on the display. '''A: ''' There have been issues using the Xilinx tools on a KDE desktop environment. For best results be sure you are using GNOME. To change the environment, click configure on the NX session login prompt, then change the drop-down box under Desktop to say GNOME. '''Q: ''' The setup.sh script is erroring when run saying either ''if: Expression Syntax'' or ''ZED_SETUP not defined''. '''A: ''' You are running the wrong shell on your terminal. Type ''bash'' , then rerun the script. ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 157 150 2015-07-21T15:58:27Z Zambreno 2 /* SDK Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. On some configurations there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 150 139 2014-11-14T19:55:45Z Vens 15 /* SDK Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. '''Fixing Cairo Error'''. Currently there is a problem when the JVM running XSDK tries to render graphics using Cairo causing the following error: <code>cairo-misc.c:380: _cairo_operator_bounded_by_source: Assertion `NOT_REACHED' failed</code>. To fix this problem we simply tell the JVM to disable rendering using Cairo by calling XSDK with the following command: <code>xsdk -vmargs -Dorg.eclipse.swt.internal.gtk.cairoGraphics=false</code>. The <code>-vmargs</code> is needed to tell Eclipse to pass the next argument to the JVM. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 139 138 2014-11-04T16:40:38Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates for my PID code. '''A: ''' Your PID code can assume a constant update rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 138 137 2014-10-29T16:24:34Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 16-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are floats, thus each is 4-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 137 136 2014-09-16T16:33:08Z Zambreno 2 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this set to "Off" (toggled forward). The upper-right switch is the trainer switch: keep this set to "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 136 135 2014-09-16T16:32:34Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this on "Off" (toggled forward). The upper-right switch is the trainer switch: keep this on "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 135 134 2014-09-16T16:32:10Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this on "Off" (toggled forward). The upper-right switch is the trainer switch: keep this on "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 134 133 2014-09-16T16:31:47Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this on "Off" (toggled forward). The upper-right switch is the trainer switch: keep this on "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 133 132 2014-09-16T16:31:24Z Zambreno 2 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; '''Q: ''' Which transmitter should I use for flight testing, and how should it be configured? '''A: ''' Note: for safety reasons, do not perform ANY flight testing without the TA or instructor present. We are using transmitter #2, also labelled as "To Quad". There are two switches of note on this transmitter. The upper-left switch is the throttle kill-switch: keep this on "Off" (toggled forward). The upper-right switch is the trainer switch: keep this on "Slave" (toggled forward) so that this can act as a flight test master kill switch. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 132 131 2014-09-10T16:44:03Z Zambreno 2 /* General Software Help */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have expressed a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 131 130 2014-09-10T16:34:38Z Zambreno 2 /* General Software Help */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have noted a preference for the older (3.5) version of the NX Client. We have archived versions for Windows, OS X, and Linux available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 130 129 2014-09-10T16:34:05Z Zambreno 2 /* General Software Help */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have noted a preference for the older (3.5) version of the NX Client. We have archived versions of these available on the class website under the [http://class.ece.iastate.edu/cpre488/resources.asp resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 129 128 2014-09-10T16:33:51Z Zambreno 2 /* General Software Help */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client]. Note, several students have noted a preference for the older (3.5) version of the NX Client. We have archived versions of these available on the class website under the [http://class.ece.iastate.edu/cpre488/resources/ resources] page. * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 128 127 2014-09-09T15:39:35Z Zambreno 2 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See the wikipedia entry on [http://en.wikipedia.org/wiki/Raster_bar Raster bar] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 127 126 2014-09-09T15:39:15Z Zambreno 2 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' When running the vga_test application, why am I only seeing green and blue bars? Where is my red channel? '''A: ''' Your VTC timing is slightly off, leading to non-blank pixels being transmitted during the horizontal and/or vertical blanking period. See [http://en.wikipedia.org/wiki/Raster_bar wiki] for an example of the effects that are possible by messing with the blanking period. Assuming you are only off by 1 pixel, the easiest solution is to tweak vga_test (and any other software application using this VGA setup) to set the first column of your 640x480 framebuffer to black. '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 126 125 2014-08-20T15:09:54Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 125 124 2014-08-20T15:09:42Z Zambreno 2 /* XPS Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 124 123 2014-08-20T15:09:17Z Zambreno 2 /* XPS Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: # You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. # You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 123 121 2014-08-20T15:08:58Z Zambreno 2 /* XPS Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== '''Multiple XPS sessions'''. When you open up XSDK, it (very quickly, nearly invisibly) copies the SDK_Export/ from your currently-open XPS project into your system_hw_platform project. This can lead to some seriously painful bugs: 1) You do a normal export from your project and open up SDK, but while working on SDK you also decide to open up a previous project to see where you might have gone wrong. 2) You open up two XPS (or two XSDK) projects to compare approaches. A bitfile / .elf mismatch can cause all sorts of problems, because at the very least you are going to be driving signals that correspond to unmapped memory regions which can lock the CPU. Keep it to 1 XPS + 1 XSDK session, and open up other files you want to simultaneously inspect outside the Xilinx tools. ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 121 119 2014-08-19T17:06:27Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 119 118 2014-04-15T14:55:23Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included <math.h>, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan. Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending an "RC channel" message. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint16_t values, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 uint16_t values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw value (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 118 117 2014-04-13T23:37:37Z Phjones 7 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I would like to record the time between GPS updates so that I can used the in my PID code. '''A: ''' For the sake of simplifying, your PID code can assume a constant update rate. Thus your PID will update at a rate of 1. This greatly simplifies the PID code. '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included math.h, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan .Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending a "RC channel" message. '''Q: ''' The GUI for interfacing with the Quad shown in class looked pretty cool. How can I find this GUI? '''A: ''' The GUI can be found here: http://code.google.com/p/multiwii/downloads/list It runs on Windows, and our quads are compatible with version 2.3. The name of the executable is MultiWiiConf.exe. You must pair the bluetooth of the Quad to your laptop in order to use this GUI. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint 16, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 unit 16 values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 117 116 2014-04-13T23:25:37Z Phjones 7 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' Why is the SDK compiler giving errors when I try to use math functions such as atan, pow, sqrt? '''A: ''' You need to make sure you have included math.h, also you need to link to the math library to your project. Here is a link that talks about this: http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan .Here is the summary: 1) right click on your application project, 2) select the C/C++ Build Settings option, 3) click on the Tool Settings tab, 4)locate the ARM Linux gcc linker-->Libraries pane, 4)add the 'm' library http://www.zedboard.org/content/problems-fpu-commands-sqrt-atan '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending a "RC channel" message. '''Q: ''' The GUI for interfacing with the Quad shown in class looked pretty cool. How can I find this GUI? '''A: ''' The GUI can be found here: http://code.google.com/p/multiwii/downloads/list It runs on Windows, and our quads are compatible with version 2.3. The name of the executable is MultiWiiConf.exe. You must pair the bluetooth of the Quad to your laptop in order to use this GUI. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint 16, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 unit 16 values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 116 115 2014-04-13T23:15:48Z Phjones 7 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster than it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending a "RC channel" message. '''Q: ''' The GUI for interfacing with the Quad shown in class looked pretty cool. How can I find this GUI? '''A: ''' The GUI can be found here: http://code.google.com/p/multiwii/downloads/list It runs on Windows, and our quads are compatible with version 2.3. The name of the executable is MultiWiiConf.exe. You must pair the bluetooth of the Quad to your laptop in order to use this GUI. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint 16, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 unit 16 values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 115 114 2014-04-13T23:14:13Z Phjones 7 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' My quad is ARMing and responding to Bluetooth commands when I have a printf placed in my "send quad commands" loop, but if I remove the printf things stop working. '''A: ''' It appears the Zedboard can send commands to the quad faster then it can process. Try placing a usleep(10000) (i.e. about 10ms) in your send loop in order to slow the Zedboard down a little. In other words, make sure there is a delay between sending a "RC channel" message. '''Q: ''' The GUI for interfacing with the Quad shown in class looked pretty cool. How can I find this GUI? '''A: ''' The GUI can be found here: http://code.google.com/p/multiwii/downloads/list It runs on Windows, and our quads are compatible with version 2.3. The name of the executable is MultiWiiConf.exe. You must pair the bluetooth of the Quad to your laptop in order to use this GUI. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint 16, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 unit 16 values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 114 113 2014-04-13T15:59:09Z Phjones 7 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' The GUI for interfacing with the Quad shown in class looked pretty cool. How can I find this GUI? '''A: ''' The GUI can be found here: http://code.google.com/p/multiwii/downloads/list It runs on Windows, and our quads are compatible with version 2.3. The name of the executable is MultiWiiConf.exe. You must pair the bluetooth of the Quad to your laptop in order to use this GUI. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint 16, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 unit 16 values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 113 112 2014-04-13T15:58:39Z Phjones 7 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' The GUI for interfacing with the Quad shown in class looked pretty cool. How can I find this GUI? '''A: ''' The GUI can be found here: http://code.google.com/p/multiwii/downloads/list It runs on Windows, and our quads are compatible with version 2.3. The name of the executable is MultiWiiConf.exe. You must pair the bluetooth of the Quad to your laptop in order to use this GUI. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint 16, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 unit 16 values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 112 111 2014-04-13T15:58:08Z Phjones 7 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' The GUI for interfacing with the Quad shown in class looked pretty cool. How can I find this GUI? '''A: ''' The GUI can be found here: [http://code.google.com/p/multiwii/downloads/list] It runs on Windows, and our quads are compatible with version 2.3. The name of the executable is MultiWiiConf.exe. You must pair the bluetooth of the Quad to your laptop in order to use this GUI. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint 16, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 unit 16 values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 111 110 2014-04-13T15:56:14Z Phjones 7 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' The GUI for interfacing with the Quad shown in class looked pretty cool. How can I find this GUI? '''A: ''' The GUI can be found here: http://code.google.com/p/multiwii/downloads/list It runs on Windows, and our quads are compatible with version 2.3. The name of the executable is MultiWiiConf.exe. You must pair the bluetooth of the Quad to your laptop in order to use this GUI. '''Q: ''' I'm sending ARM commands to the Quad, but the Quad is not ARMing (i.e. the red light on the Quad's main board does not come on, which will often start the blades spinning, but not always). '''A: ''' There are several possible issues: 1) The channel commands are 2-bytes each, when you write each channel into your communication buffer you need to write the least significant byte first, 2) You should be continuously sending commands to the quad (faster than once per second), if you just send a single ARM command the quad will not respond, 3) Have your Roll, Pitch, AUX1, AUX2, AUX3, AUX4 set to about 1500, this is equivalent to having an RC controller stick dead-center. '''Q: ''' For the set RC channel command, the multiWii command wiki says to send 16 uint 16, but only shows 8 channels. I'm confused. '''A: ''' The multiWii website has a typo. Since you are only sending 8 channels, it should say send 8 unit 16 values. '''Q: ''' It's great that the GPS client will send my Zedboad X,Y,Z,Yaw information, but what is the format.... '''A: ''' When your Zedboard requests GPS information from the client, the client will respond with a 32-byte buffer of data. Each X,Y,Z,Yaw (in that order) are doubles, thus each is 8-bytes long. To verify you get the byte order correct you will want to send a debug message back to the GPS client that displays the GPS values that you received. '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 110 109 2014-04-11T17:02:18Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and the [[Project Page]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 109 106 2014-04-11T17:02:01Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! See below for relevant information for the weekly labs, and [[Project Page here]] for information regarding the course project. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 106 104 2014-04-11T16:17:43Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. [[Project Page]] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] 104 103 2014-04-11T16:16:49Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. [[Project Page]] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 103 102 2014-04-11T15:05:56Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 102 101 2014-04-07T18:33:24Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' I'm initializing my UART0 correctly with XUartPs_CfgInitialize(), but when I call XUartPS_RecvByte(), I am often receiving garbage data. What am I doing wrong? '''A: ''' There are several possible issues at this stage of MP-4. 1) Check that you are initializing your pointer to the XUartPs_Config structure properly using XUartPs_LookupConfig(). 2) Either call XUartPs_SetBaudRate() or XUartPs_EnableUart(). 3) Explicitly reset the TX and RX data paths in the UART0, by setting the appropriate bits in the control register to '1'. This last part is probably a Xilinx bug, since the system reset should also reset the UARTs. '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- |} 101 100 2014-04-04T15:36:37Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- |} 100 99 2014-04-02T17:02:27Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *2 X Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *2 X PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *3 X CON4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *2 X PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *2 X PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] *2 X PmodACL2 - [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf 3-Axis Digital Accelerometer] *2 X Regulator1 - [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Voltage Regulator] *2 X PmodTPH2 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 12-Pin Test Point Header] *2 X CON3 - [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf Servo Connector] *2 X PmodLS1 - [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf Infrared Light Detector] *2 X PmodJSTK - [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf Joystick] *2 X PmodDPOT - [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf Digital Potentiometer] *2 X PmodUSBUART - [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf USB to UART Converter] *2 X PmodMIC - [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC Microphone] *PmodHB3 - [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf 2A H-Bridge] *2 X PmodKYPD - [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf Keypad] *2 X PmodENC - [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf Rotary Encoder] *PmodGYRO - [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf 3-Axis Digital Gyroscope] *PmodAMP1 - [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf Speaker/Headphone Amplifier] *2 X PmodSSD - [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf Seven-Segment Display] *DA1 Module - [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf Digital to Analog Convert] *PmodSTEP - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP Stepper Motor Controller] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 99 98 2014-04-02T17:00:24Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *2 X Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *2 X PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *3 X CON4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *2 X PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *2 X PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] *2 X PmodACL2 - [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf 3-Axis Digital Accelerometer] *2 X Regulator1 - [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Voltage Regulator] *2 X PmodTPH2 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 12-Pin Test Point Header] *2 X CON3 - [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf Servo Connector] *2 X PmodLS1 - [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf Infrared Light Detector] *2 X PmodJSTK - [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf Joystick] *2 X PmodDPOT - [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf Digital Potentiometer] *2 X PmodUSBUART - [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf USB to UART Converter] *2 X PmodMIC - [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC Microphone] *PmodHB3 - [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf 2A H-Bridge] *2 X PmodKYPD - [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf Keypad] *2 X PmodENC - [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf Rotary Encoder] *PmodGYRO - [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf 3-Axis Digital Gyroscope] *PmodAMP1 - [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf Speaker/Headphone Amplifier] *2 X PmodSSD - [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf Seven-Segment Display] *DA1 Module - [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf Digital to Analog Convert] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] *2 X Undocumented Stepper Motor Controller - Made by Team Gen-X Micro 98 97 2014-04-02T16:59:11Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |<tt>81:eb:b6:86:e1:d4</tt> |- |3 |<tt>81:eb:b6:81:b3:6c</tt> |- |4 |<tt>81:e9:9f:00:f1:a3</tt> |- |5 |<tt>81:eb:ad:e7:a8:ce</tt> |- |6 |<tt>81:eb:ad:cd:9a:1e</tt> |- |7 |<tt>81:eb:b6:90:6a:6d</tt> |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *2 X Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *CON4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] *PmodACL2 - [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf 3-Axis Digital Accelerometer] *Regulator1 - [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Voltage Regulator] *PmodTPH2 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 12-Pin Test Point Header] *CON3 - [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf Servo Connector] *PmodLS1 - [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf Infrared Light Detector] *PmodJSTK - [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf Joystick] *PmodDPOT - [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf Digital Potentiometer] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] *2 X Undocumented Stepper Motor Controller - Made by Team Gen-X Micro 97 96 2014-04-02T16:58:42Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC <tt> |- |1 |81:eb:b6:8b:79:13</tt> |- |2 |81:eb:b6:86:e1:d4 |- |3 |81:eb:b6:81:b3:6c |- |4 |81:e9:9f:00:f1:a3 |- |5 |81:eb:ad:e7:a8:ce |- |6 |81:eb:ad:cd:9a:1e |- |7 |81:eb:b6:90:6a:6d |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *2 X Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *CON4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] *PmodACL2 - [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf 3-Axis Digital Accelerometer] *Regulator1 - [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Voltage Regulator] *PmodTPH2 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 12-Pin Test Point Header] *CON3 - [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf Servo Connector] *PmodLS1 - [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf Infrared Light Detector] *PmodJSTK - [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf Joystick] *PmodDPOT - [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf Digital Potentiometer] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] *2 X Undocumented Stepper Motor Controller - Made by Team Gen-X Micro 96 95 2014-04-02T16:58:27Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |<tt>81:eb:b6:8b:79:13</tt> |- |2 |81:eb:b6:86:e1:d4 |- |3 |81:eb:b6:81:b3:6c |- |4 |81:e9:9f:00:f1:a3 |- |5 |81:eb:ad:e7:a8:ce |- |6 |81:eb:ad:cd:9a:1e |- |7 |81:eb:b6:90:6a:6d |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *2 X Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *CON4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] *PmodACL2 - [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf 3-Axis Digital Accelerometer] *Regulator1 - [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Voltage Regulator] *PmodTPH2 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 12-Pin Test Point Header] *CON3 - [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf Servo Connector] *PmodLS1 - [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf Infrared Light Detector] *PmodJSTK - [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf Joystick] *PmodDPOT - [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf Digital Potentiometer] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] *2 X Undocumented Stepper Motor Controller - Made by Team Gen-X Micro 95 94 2014-04-02T16:57:38Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |1 |81:eb:b6:8b:79:13 |- |2 |81:eb:b6:86:e1:d4 |- |3 |81:eb:b6:81:b3:6c |- |4 |81:e9:9f:00:f1:a3 |- |5 |81:eb:ad:e7:a8:ce |- |6 |81:eb:ad:cd:9a:1e |- |7 |81:eb:b6:90:6a:6d |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *2 X Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *CON4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] *PmodACL2 - [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf 3-Axis Digital Accelerometer] *Regulator1 - [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Voltage Regulator] *PmodTPH2 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 12-Pin Test Point Header] *CON3 - [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf Servo Connector] *PmodLS1 - [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf Infrared Light Detector] *PmodJSTK - [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf Joystick] *PmodDPOT - [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf Digital Potentiometer] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] *2 X Undocumented Stepper Motor Controller - Made by Team Gen-X Micro 94 93 2014-04-02T16:36:19Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *2 X Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *CON4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] *PmodACL2 - [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf 3-Axis Digital Accelerometer] *Regulator1 - [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Voltage Regulator] *PmodTPH2 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 12-Pin Test Point Header] *CON3 - [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf Servo Connector] *PmodLS1 - [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf Infrared Light Detector] *PmodJSTK - [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf Joystick] *PmodDPOT - [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf Digital Potentiometer] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] *2 X Undocumented Stepper Motor Controller - Made by Team Gen-X Micro 93 92 2014-04-02T16:30:57Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart_1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 92 91 2014-04-02T16:21:30Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 91 90 2014-04-02T16:19:47Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="25%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 90 89 2014-04-02T16:19:35Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| width="85%" style="text-align:center;" ! Quad-ID ! Bluetooth MAC |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 89 88 2014-04-02T16:15:57Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| ! style="text-align:center;"| Quad-ID ! Bluetooth MAC |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 88 87 2014-04-02T16:15:39Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| ! style="text-align:center;"| Quad-ID ! Bluetooth MAC |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |0 |00:00:00:00:00 |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 87 86 2014-04-02T16:14:54Z Zambreno 2 /* MP-4 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| ! style="text-align:center;"| Quad-ID ! Bluetooth MAC |- |Orange |10 |- |Bread |4 |- |Butter |1 |- |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 86 85 2014-04-02T16:11:49Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart1. '''Q: ''' How can I determine the Bluetooth MAC address for my quad? '''A: ''' You can connect to it using your laptop (if it has Bluetooth) and view the MAC address that way. Or, lookup the corresponding entry in this table: {| class="wikitable" !colspan="6"|Shopping List |- |rowspan="2"|Bread & Butter |Pie |Buns |Danish |colspan="2"|Croissant |- |Cheese |colspan="2"|Ice cream |Butter |Yogurt |} ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 85 84 2014-04-02T16:09:42Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-4 Frequently Asked Questions (FAQ)== '''Q: ''' After adding UART0, how can I continue to print out debug messages to PuTTy? '''A: ''' Since we are using both of the PS7 UARTs in MP-4, you will need to be careful with regards to what STDIN and STDOUT are pointing to (and serial communication in general). Right-click your application's BSP, and select "Modify BSP Settings". Under the "standalone" option, set both stdin and stdout to point to ps7_uart1. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 84 83 2014-04-02T16:09:05Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection (the black boxes)=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-Bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-Bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-Bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-Port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-Channel ADC] ===Digilent (the red bags)=== *PmodRS232 - [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf RS232 Converter] *Digilent Switch Module - [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf 4-Switch Module] *PS2 Module - [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] *Con4 - [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf RCA to 6-Pin] - needs ADC for connection to ZedBoard *PmodGPS - [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf GPS Receiver] *PmodDIP - [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf Dual Inline Package] *PmodWiFi - [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf WiFi Radio Transceiver] *PmodBB - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB Wirewrap/Breadboard] *PmodRJ45 - [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 RJ45 to FPGA Connector Pair] ===Miscellaneous=== *OPB704WZ - [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf Reflective Object Sensor] 83 82 2014-04-02T15:34:12Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== ==List of available PMODs== ===Maxim Integrated - Analog Essentials Collection=== *MAX11205 - [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf 16-bit ADC] *MAX44000 - [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf Proximity Sensor] *MAX9611 - [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf Current Sensor with 12-bit ADC and OpAmp/Comparator] *DS1086L - [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf Oscillator] *MAX5487 - [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf Digital Potentiometer] *MAX31855 - [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf Thermocouple to Digital Converter] *MAX5216 - [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf 16-bit ADC] *MAX14840E - [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf 40 Mbps RS-485 Half-Duplex Transceiver] *DS3231M - [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf I2C Real-Time Clock] *MAX4824 - [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf 8-Channel Relay Driver] *MAX31723 - [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf Temperature Sensor] *MAX14850 - [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf SPI Isolator] *MAX3232 - [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf RS232 Transceiver] *MAX7304 - [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf 16-port IO] *MAX5825 - [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf 8-channel ADC] 82 81 2014-03-13T19:50:15Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 81 80 2014-03-13T19:49:38Z Zambreno 2 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 80 79 2014-03-12T21:42:26Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 79 78 2014-03-12T21:42:19Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' asdf When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 78 77 2014-03-12T21:42:06Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 77 76 2014-03-12T21:41:56Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== ''Auto-loading a design using the sdcard'' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 76 75 2014-03-12T21:41:46Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''' When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 75 74 2014-03-12T21:41:30Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard''': When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''': If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 74 73 2014-03-12T21:41:13Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. '''Board Jumpers''' If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 73 72 2014-03-12T21:41:09Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ""Board Jumpers"" If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 72 71 2014-03-12T21:40:54Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ""Board Jumpers"" If your board is not booting an SD card, you may have an engineering sample board. Check to see if JP6 (just below the top PMOD on the left side of the board) has a jumper connect. The engineering sample boards require this jumper to boot from SD Card. Furthermore, if you can boot to linux but your usb port doesn't appear to be working, be sure that JP2 is jumped. This provides power to the usb +5v rail. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 71 70 2014-03-12T21:40:22Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 70 69 2014-03-12T21:39:54Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 69 68 2014-03-12T21:39:29Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Hardware Design Help== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==Project Ideas== 68 67 2014-03-12T21:38:34Z Zambreno 2 /* Useful Documentation */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 67 66 2014-03-12T21:36:45Z Zambreno 2 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program: [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 66 65 2014-03-12T21:36:18Z Zambreno 2 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program [http://www.extraputty.com/snapshots/Download/thanksputty.html link]. Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 65 64 2014-03-12T21:35:24Z Zambreno 2 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, booting Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes, yes there is! You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program (http://www.extraputty.com/snapshots/Download/thanksputty.html). Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 64 63 2014-03-12T21:33:49Z Bvermeer 5 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, boot Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes there is. You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program (http://www.extraputty.com/snapshots/Download/thanksputty.html). Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program in Linux and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 63 62 2014-03-12T21:33:08Z Bvermeer 5 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, boot Linux back up, and then testing my driver. Is there a better way? '''A: ''' Yes there is. You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program (http://www.extraputty.com/snapshots/Download/thanksputty.html). Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 62 61 2014-03-12T21:32:39Z Bvermeer 5 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. '''Q: ''' I'm sick of constantly taking out the SD card, copying over my driver, starting back up Linux, and then testing my driver. Is there a better way? '''A: ''' Yes there is. You can transfer files to Linux using the XModem protocol. Unfortunately, the version of PuTTY installed on the computers doesn't support XModem. First, download the ExtraPuTTY program (http://www.extraputty.com/snapshots/Download/thanksputty.html). Unzip ExtraPuTTY and run the putty.exe program in it. To transfer a file to Linux, first run the rx program and give it the file name you want your transferred file saved as (rx [filename]). A "C" will be displayed on the terminal. Then, open the "File Transfer" -> "XModem1K" -> "Send" menu on ExtraPuTTY and choose the file you want to transfer. A few seconds later, the file will be transferred! ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 61 60 2014-03-12T14:27:19Z Zambreno 2 /* MP-3 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A reasonable rule is to build the kernel with the same number of threads that your computer has cores. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 60 59 2014-03-05T22:21:27Z Bvermeer 5 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be "make UIMAGE_LOADADDR=0x8000 uImage -j16". A general rule is to build the kernel with the same number of threads that your computer has cores. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 59 58 2014-03-05T22:20:44Z Bvermeer 5 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-3 Frequently Asked Questions (FAQ)== '''Q: ''' How can I speed up the SLOW Linux kernel compile process? '''A: ''' Add a -j[number of threads] flag to the command where you compile the kernel. For example, if you want to build the kernel with 16 threads, the command would be make UIMAGE_LOADADDR=0x8000 uImage -j16. A general rule is to build the kernel with the same number of threads that your computer has cores. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 58 57 2014-03-02T03:53:47Z Zambreno 2 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been using for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 4 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 57 56 2014-02-26T19:24:27Z Zambreno 2 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheets for the RGB2YCrCb and Chroma Resample components found in the MP-2 assignment. Also, take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf]. '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 56 55 2014-02-26T18:45:41Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' Some good information on this topic can be found in the datasheet for the RGB2YCrCb and Chroma Resample component found in the MP2 assignment, and take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf] '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 55 54 2014-02-26T17:51:48Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' See the datasheet for the RGB2YCrCb component found in the MP2 assignment, and take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf ch03.pdf] '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 54 53 2014-02-26T17:47:39Z Zambreno 2 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' See the datasheet for the RGB2YCrCb component found in the MP2 assignment, and take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf] '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 53 52 2014-02-26T17:43:29Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' How does converting from RGB to YCbCr work? '''A: ''' See the datasheet for the RGB2YCrCb component found in the MP2 assignment, and take a look at this document for more information about theory of operation [http://www.compression.ru/download/articles/color_space/ch03.pdf] '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 52 51 2014-02-26T17:41:03Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: '''How does converting from RGB to YCbCr work? See the datasheet for the RGB2YCrCb component found in the MP2 assignment, and take a look at this document for more information about theory of operation [www.compression.ru/download/articles/color_space/ch03.pdf] '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 51 50 2014-02-26T16:04:33Z Zambreno 2 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 50 49 2014-02-26T16:04:14Z Zambreno 2 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 49 48 2014-02-26T16:03:51Z Zambreno 2 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' What is the starting color sensor for the Bayer pattern we are applying? '''A: ''' Look at the datasheets for both the CFA (the hardware module that applies the Bayer filter) and the VITA sensor. '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 48 47 2014-02-25T17:49:19Z Zambreno 2 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. You can either create your own 3.10.a BSP for the FSBL project, or directly fix the compile errors: * The QSPI library is generating most of the errors, so replace every instance of "XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR" with "XPAR_PS7_QSPI_FSBL_HACK", or something else that is not currently defined. There are 3 places in the FSBL code to make this change. * The XDcfg_GetPsVersion() function isn't defined in the 3.06.a standalone BSP. In function GetSiliconVersion(), directly set variable "Silicon_Version" to SILICON_VERSION_3_1, and comment out the call to XDcfg_GetPsVersion(). We will be integrating the camera_app code into the MP-3 FSBL directly, so upgrading the standalone BSP won't work at that point and you'll have to fix the compile errors. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 47 46 2014-02-25T17:42:46Z Zambreno 2 /* MP-2 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] '''Q: ''' We're seeing multiple compile errors when creating the First Stage Boot Loader (FSBL) design. It's worked all semester long - what gives? '''A: ''' The MP-2 FMC-IMAGEON infrastructure only works with an older version of the "standalone" Xilinx library we have been use for our bare-metal software development. That version (3.06.a) is not fully API-compatible with the v14.6 FSBL code. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 46 45 2014-02-17T22:59:43Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-2 Frequently Asked Questions (FAQ)== '''Q: ''' I'm having trouble understanding the relationship between the video timing controller(s), video in/out, and the VDMA. What's a good resource to look through? '''A: ''' The AXI4-Stream Video IP and System Design Guide provides a very nice overview of how these components work together: [http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ug934_axi_videoIP.pdf] ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 45 44 2014-02-14T18:12:33Z Tborglum 8 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. '''Q: ''' My simulation has a "component instance is not bound" error. What does this mean? Why can't I see the signals of my user_logic component? '''A: ''' This error occurs because the user_logic file is not in the working library of the simulation and it does not recognize the interface or because the generics and ports of the instantiated component do not EXACTLY match the declaration. To fix this problem you need to include the library of the component you want to use; in this case the library is "axi_ppm_v1_00_a" and the part we want from it is "user_logic". To use this library in your created testbench design, you can take the following 2 lines of code from the top of the file in axi_ppm.vhd: library axi_ppm_v1_00_a; use axi_ppm_v1_00_a.user_logic; ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 44 43 2014-02-12T19:54:39Z Tborglum 8 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. '''Q: ''' How do I use the logic level converters? '''A: ''' See the [https://learn.sparkfun.com/tutorials/bi-directional-logic-level-converter-hookup-guide/all SparkFun Logic Level Converter Guide] to understand the interface. For the cables we use, black/brown is ground, red is high, and other colors are data lines. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 43 42 2014-02-07T18:54:29Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] [http://class.ece.iastate.edu/cpre583/HW/HW1/Tools_overview.ppt Quick ISE/Modelsim Overview (ppt) (Note: Was made for an older version of the tools, but should help give you a better understanding of the tools in general)] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 42 41 2014-02-07T18:35:12Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding: My Design Works in Simulation, but not in Hardware!!!" (ppt)] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes (pdf Abbreviated version)] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 41 40 2014-02-07T18:31:42Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview] [http://class.ece.iastate.edu/cpre488/resources/Details_VHDL_common_mistakes.ppt Common VHDL Mistakes "Avoiding My Design Works in Simulation, but not in Hardware] [http://class.ece.iastate.edu/cpre488/resources/Common_VHDL_mistakes.pdf Common VHDL Mistakes] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 40 39 2014-02-07T18:27:33Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://class.ece.iastate.edu/cpre488/resources/VHDL_Overview.ppt Dr. Jones' Practical VHDL Overview] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 39 38 2014-02-07T18:21:31Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''':<BR /> [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] '''Tools''':<BR /> [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 38 37 2014-02-07T18:07:03Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== '''VHDL''': [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] '''Tools''': [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 37 36 2014-02-07T17:15:45Z Zambreno 2 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. '''Q: ''' What is the MPD file format? How do I add my external signals to the auto-generated IP core? '''A: ''' Check out the EDK [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - the MPD file syntax starts on page 27. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 36 35 2014-02-07T17:14:37Z Zambreno 2 /* Useful Documentation */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 35 34 2014-02-07T17:09:50Z Tborglum 8 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL Reference Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - contains MPD file syntax starting on page 27 [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 34 33 2014-02-07T17:01:02Z Tborglum 8 Added helpful documentation links wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== [http://www.freerangefactory.org/dl/free_range_vhdl.pdf Free Range VHDL reference guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf EDK User Guide] [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf Platform Specification Reference Manual] - contains MPD file syntax starting on page 27 [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf EDK Profiling Guide] ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 33 32 2014-02-07T16:58:24Z Tborglum 8 Added helpful documentation links wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf] EDK User Guide) ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf] Platform Specification Reference Manual) - contains MPD file syntax starting on page 27 ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf] EDK Profiling Guide) ([http://www.freerangefactory.org/dl/free_range_vhdl.pdf] VHDL reference guide) ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 32 31 2014-02-07T16:58:10Z Tborglum 8 Added helpful documentation links wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Useful Documentation== ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/est_rm.pdf] EDK User Guide) ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/psf_rm.pdf] Platform Specification Reference Manual) - contains MPD file syntax starting on page 27 ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/edk_prof.pdf] EDK Profiling Guide) ([http://www.freerangefactory.org/dl/free_range_vhdl.pdf] VHDL reference guide) ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 31 30 2014-02-05T23:16:40Z Zambreno 2 /* MP-1 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad receiver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] '''Q: ''' How do I get my changes to my axi_ppm MPD file to be reflected in the XPS project? '''A: ''' XPS caches all the pcore metadata when it first launches. Select "Project -> Rescan User Repositories" to see your changes. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 30 29 2014-02-05T18:15:49Z Phjones 7 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-1 Frequently Asked Questions (FAQ)== '''Q: ''' How do I bind a transmitter to the quad reciver? '''A: ''' Follow this YouTube Link [http://www.youtube.com/watch?v=oX4I_gNecfk] ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 29 28 2014-02-05T00:20:35Z Dnhushak 3 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 28 26 2014-02-05T00:20:16Z Dnhushak 3 wikitext text/x-wiki $wgLogo = "http://wikis.ece.iastate.edu/cpre488/index.php/Image:Link.png" Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 26 25 2014-02-01T19:39:29Z Zambreno 2 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but in any case the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 25 24 2014-02-01T19:39:04Z Zambreno 2 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. '''Q: ''' This assignment is too hard! '''A: ''' Not really a question, but the sentiment is understood. MP-0 is about learning more about the platform and the tools, and it accomplishes that goal. The first design is always the most frustrating, and in MP-0 we wanted to introduce as many Xilinx EDK features as possible, including some of the bugs. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 24 23 2014-02-01T19:37:00Z Zambreno 2 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' How do I get a 12-bit RGB signal? The settings in axis_vid_out seem to provide separate channels for Red, Blue, and Green, and there's no 4-bit option there. '''A: ''' For our purposes, the vid_out doesn't really need any knowledge of the data format, other than it should be taking in the 16-bit signal off the AXI stream and outputting 12-bit pixels. The ug934_axi_videoIP.pdf guide provides a nice overview of the different video out modes, and how you could configure a 12-bit signal. '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 23 22 2014-02-01T19:34:25Z Zambreno 2 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". '''Q: ''' What do a correct v_sync and h_sync look like? '''A: ''' Check the two links in the prelab portion of MP-0. Your signals, including timing information and pulse polarity, should match exactly what is shown in the digilent datasheet. '''Q: ''' I don't understand whether or not I need to connect signal ''X'' in component ''Y''. '''A: ''' Check the datasheets, either directly in XPS or in the docs/IP/ sub-directory of your MP-0 install. For example, pg044_v_axis_vid_out.pdf provides nice, clear architectural diagrams for the axis_vid_out component. For example, do you need to connect the aclk port to something? Check the diagram on page 8. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 22 21 2014-02-01T19:29:30Z Zambreno 2 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. '''Q: ''' I can't see all the signals that are being discussed in the MP-0 document. What gives? '''A: ''' Even in the "Ports" tab, XPS hides some connections if they have a default assignment. Click the "Filter" button on the right of the "Ports" tab, and select all the options, including "Default". ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 21 20 2014-02-01T19:27:24Z Zambreno 2 /* MP-0 Frequently Asked Questions (FAQ) */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' I'm not seeing anything on my VGA monitor, and I've hooked up everything correctly (as far as I can tell). What should I do next? '''A: ''' There are three main points of failure in the design: the v_tc timing controller, the axi_vdma module, and the video out. Connect some internal signals in your design (e.g. the vTIMING_OUT) to a PMOD port so that you can probe them. Keep in mind that the vid_out only will start transmitting when it synchronizes the data coming in on the AXI video stream with the timing data. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 20 19 2014-02-01T19:23:40Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==MP-0 Frequently Asked Questions (FAQ)== '''Q: ''' '''A: ''' ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 19 18 2014-01-29T22:01:41Z Zambreno 2 /* SDK Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== '''Matching a BSP to a software project'''. When an XPS system is exported to SDK, a Board Support Package ([http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/SDK_Doc/concepts/sdk_c_bsp_internal.htm BSP]) is created that provides drivers for the various peripherals in your design. Any new software projects will be based on this BSP, but on occasion, any existing (or newly imported) projects will still access older BSPs. This is a common cause of missing header files during compilation. To resolve this, right-click on your software project in XSDK, and select "Change Referenced BSP". Selecting the appropriate BSP will update your project to look at the right headers and libraries. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 18 17 2014-01-16T17:28:10Z Zambreno 2 /* ZedBoard Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, first select that application, then select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 17 16 2014-01-08T22:09:05Z Zambreno 2 /* ZedBoard Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK, name the project zynq_fsbl, and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 16 15 2014-01-08T22:08:03Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==XPS Tricks and Tips== ==SDK Tricks and Tips== ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] ==Project Ideas== 15 14 2014-01-08T22:05:41Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==General Software Help== '''Remote Linux access''': * Download and install [http://www.nomachine.com/download.php NX Client] * Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] 14 13 2014-01-08T22:05:28Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. # A system.bit file created during the conventional XPS build process. # An application that will be loaded after the bitfile programming. Xilinx provides a template for generating the FSBL project. Select "New -> Application Project" in XSDK and choose the First Stage Bootloader as one of the project template. You should not have to change any of the files in the project, and it will automatically build. Assuming you then have some other application you would like to load during the boot process, select "Xilinx Tools -> Create Boot Image". This utility should automatically find the three files needed to generate the BOOT.BIN file. Select where you'd like the output files to be generated. Once the .bin file is generated, rename it to BOOT.BIN and copy to your sdcard. ==General Software Help== '''Remote Linux access''': - Download and install [http://www.nomachine.com/download.php NX Client] - Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] 13 12 2014-01-08T22:01:02Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. ==General Software Help== '''Remote Linux access'''. # Download and install [http://www.nomachine.com/download.php NX Client] # Connect to one of the standard remotely accessible Linux machines: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] 12 11 2014-01-08T21:53:27Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==ZedBoard Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. ==General Software Help== '''Remote Linux access'''. Follow # Download and install [http://www.nomachine.com/download.php NX Client]. Convey machine is for testing you projects on the actual hardware only. However, 90% of the time you should be using any of the machines listed below for development. Also, standard remotely accessible ISU Linux machines should be set up for doing development for the Convey system. You can find a list of those machines here: [http://it.eng.iastate.edu/remote/ ISU Remote Access Servers] 11 10 2014-01-08T21:50:43Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==XSDK Tricks and Tips== '''Auto-loading a design using the sdcard'''. When jumpers MIO 4 and MIO 5 on the ZedBoard are shorted to 3v3, the board looks for a BOOT.BIN file in the top-level directory of the sdcard. The BOOT.BIN needs to contain the following three files, in this order: # A First Stage Boot Loader ([http://www.wiki.xilinx.com/Build+FSBL FSBL]) executable that checks system configuration registers and programs the programmable logic with the appropriate bitfile. == ZedBoard Tricks and Tips == 10 9 2014-01-08T21:46:45Z Zambreno 2 /* Design Flow Tricks and Tips */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==XSDK Tricks and Tips== '''Auto-loading a design using the sdcard''' == ZedBoard Tricks and Tips == 9 8 2014-01-08T21:45:55Z Zambreno 2 /* XSDK */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. == Design Flow Tricks and Tips == ===XSDK=== * Auto-loading a design using the sdcard == ZedBoard Tricks and Tips == 8 7 2014-01-08T21:44:39Z Zambreno 2 /* XSDK */ wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. == Design Flow Tricks and Tips == ===XSDK=== * Test == ZedBoard Tricks and Tips == 7 6 2014-01-08T21:43:01Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. == Design Flow Tricks and Tips == ===XSDK=== == ZedBoard Tricks and Tips == 6 5 2014-01-08T21:41:51Z Zambreno 2 wikitext text/x-wiki Welcome to the main wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. Also, as you discover new tips and tricks, consider contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. == Design Flow Tricks and Tips == <!--T:1--> ===XSDK=== <!--T:12--> == ZedBoard Tricks and Tips == 5 4 2014-01-08T21:40:16Z Zambreno 2 wikitext text/x-wiki Welcome to the Wiki page for CprE 488! We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. As you discover new tips and tricks, consider also contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. == Design Flow Tricks and Tips == ===XSDK=== == ZedBoard Tricks and Tips == 4 3 2014-01-08T21:37:08Z Zambreno 2 wikitext text/x-wiki Welcome to the Wiki page for CprE 488. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. As you discover new tips and tricks, consider also contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [http://www.mediawiki.org/wiki/Help:Editing_pages MediaWiki] page for further details on how to edit. ==Categories== 3 2 2014-01-08T21:34:00Z Zambreno 2 wikitext text/x-wiki Welcome to the Wiki page for CprE 488. We hope that, as this wiki develops, you will find useful information as you work on the CprE 488 labs. As you discover new tips and tricks, consider also contributing as well. Editing is very straightforward - click the "log in" link in the upper right-hand corner and use your usual university ID and password. Please see the [[editing]] page for further details. ==Categories== 2 1 2014-01-02T14:22:36Z Zambreno 2 Removing all content from page wikitext text/x-wiki 1 2014-01-02T14:19:14Z MediaWiki default 0 wikitext text/x-wiki <big>'''MediaWiki has been successfully installed.'''</big> Consult the [http://meta.wikimedia.org/wiki/Help:Contents User's Guide] for information on using the wiki software. == Getting started == * [http://www.mediawiki.org/wiki/Manual:Configuration_settings Configuration settings list] * [http://www.mediawiki.org/wiki/Manual:FAQ MediaWiki FAQ] * [https://lists.wikimedia.org/mailman/listinfo/mediawiki-announce MediaWiki release mailing list] 0 4 181 2017-02-22T16:13:54Z Imciner2 12 Created page with " == u-boot compilation == No non-standard packages required. == Kernel compilation == === make menuconfig === Requires: * ncurses-devel === make uImage === Requires: * u..." wikitext text/x-wiki == u-boot compilation == No non-standard packages required. == Kernel compilation == === make menuconfig === Requires: * ncurses-devel === make uImage === Requires: * u-boot-tools 8eb9a5fc8843ddefe1f2484abcc5fac41fdb2d1d 0 3 190 189 2017-04-21T16:43:37Z Jpbush 23 /* List of available PMODs and other project components */ wikitext text/x-wiki [[Main Page]] ==Spring 2017 Projects ([https://iastate.box.com/cpre488-s2017 Videos])== * A1 - FPGA-Based MIDI Controller * A2 - FPGA-Based Digital Synthesizer * A3 - Advanced USB Turret Controller * A4 - Image-Controlled Pong and Tic-Tac-Toe * A5 - HDMI Image Splitter * B1 - Hardware Accelerated Conway's Game of Life * B2 - Audio Source Localizer * B3 - Networked NES Emulators * B4 - Zedboard SNES Emulator * B5 - Bluetooth Heart Rate Monitoring * B6 - Zedboard Audio using a Bluetooth Speaker * C1 - Smart Home System using Zedboards * C2 - Hardware Acceleration of Convolutional Neural Networks * C3 - Zedboard-Based Oscilloscope * C4 - Secure Communication Between Zedboards * C5 - Remote Camera Security System ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [https://reference.digilentinc.com/_media/pmod:pmod:pmodAD1_rm.pdf PmodAD1] || Digilent || 1 || 12-bit ADC |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon3/pmodcon3_rm.pdf PmodCON3] || Digilent || 2 || Servo Connector |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon4/pmodcon4_rm.pdf PmodCON4] || Digilent || 3 || RCA to 6-Pin |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodda1/pmodda1_rm.pdf PmodDA1] || Digilent || 1 || Digital to Analog Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodswt/pmodswt_rm.pdf PmodSWT] || Digilent || 2 || 4-Switch Module |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodacl2/pmodacl2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [https://reference.digilentinc.com/_media/pmodamp1/pmodamp1_rm_revb.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbb/pmodbb_rm.pdf PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddip/pmoddip_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddpot/pmoddpot_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodenc/pmodenc_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgps/pmodgps_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgyro/pmodgyro_rm.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodhb3/pmodhb3_rm.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodjstk/pmodjstk_rm.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodkypd/pmodkypd_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodls1/pmodls1_rm.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [https://reference.digilentinc.com/_media/pmod:pmod:pmodMIC_rm.pdf PmodMIC] || Digilent || 2 || Microphone |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodrj45/pmodrj45_rm.pdf PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodrs232/pmodrs232_rm.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodssd/pmodssd_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodstep/pmodstep_rm.pdf PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodtph2/pmodtph2_rm.pdf PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodusbuart/pmodusbuart_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodwifi/pmodwifi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodps2/pmodps2_rm.pdf PmodPS2] || Digilent || 2 || PS2 Module |- | [https://reference.digilentinc.com/_media/pmodreg1/pmodreg1_rm.pdf PmodReg1] || Digilent || 2 || Voltage Regulator |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbtn/pmodbtn_rm.pdf PmodBTN] || Digilent || 1 || 4 User Pushbutton |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} 867d9b51680443922f867f06dfe60456508e3f16 189 188 2017-04-21T16:42:19Z Jpbush 23 /* List of available PMODs and other project components */ wikitext text/x-wiki [[Main Page]] ==Spring 2017 Projects ([https://iastate.box.com/cpre488-s2017 Videos])== * A1 - FPGA-Based MIDI Controller * A2 - FPGA-Based Digital Synthesizer * A3 - Advanced USB Turret Controller * A4 - Image-Controlled Pong and Tic-Tac-Toe * A5 - HDMI Image Splitter * B1 - Hardware Accelerated Conway's Game of Life * B2 - Audio Source Localizer * B3 - Networked NES Emulators * B4 - Zedboard SNES Emulator * B5 - Bluetooth Heart Rate Monitoring * B6 - Zedboard Audio using a Bluetooth Speaker * C1 - Smart Home System using Zedboards * C2 - Hardware Acceleration of Convolutional Neural Networks * C3 - Zedboard-Based Oscilloscope * C4 - Secure Communication Between Zedboards * C5 - Remote Camera Security System ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [https://reference.digilentinc.com/_media/pmod:pmod:pmodAD1_rm.pdf] || Digilent || 1 || 12-bit ADC |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon3/pmodcon3_rm.pdf PmodCON3] || Digilent || 2 || Servo Connector |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon4/pmodcon4_rm.pdf PmodCON4] || Digilent || 3 || RCA to 6-Pin |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodda1/pmodda1_rm.pdf PmodDA1] || Digilent || 1 || Digital to Analog Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodswt/pmodswt_rm.pdf PmodSWT] || Digilent || 2 || 4-Switch Module |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodacl2/pmodacl2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [https://reference.digilentinc.com/_media/pmodamp1/pmodamp1_rm_revb.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbb/pmodbb_rm.pdf PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddip/pmoddip_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddpot/pmoddpot_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodenc/pmodenc_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgps/pmodgps_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgyro/pmodgyro_rm.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodhb3/pmodhb3_rm.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodjstk/pmodjstk_rm.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodkypd/pmodkypd_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodls1/pmodls1_rm.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [https://reference.digilentinc.com/_media/pmod:pmod:pmodMIC_rm.pdf PmodMIC] || Digilent || 2 || Microphone |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodrj45/pmodrj45_rm.pdf PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodrs232/pmodrs232_rm.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodssd/pmodssd_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodstep/pmodstep_rm.pdf PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodtph2/pmodtph2_rm.pdf PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodusbuart/pmodusbuart_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodwifi/pmodwifi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodps2/pmodps2_rm.pdf PmodPS2] || Digilent || 2 || PS2 Module |- | [https://reference.digilentinc.com/_media/pmodreg1/pmodreg1_rm.pdf PmodReg1] || Digilent || 2 || Voltage Regulator |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbtn/pmodbtn_rm.pdf PmodBTN] || Digilent || 1 || 4 User Pushbutton |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} aa1ee08fa374cd5286468ca285fec1e60fee29f4 188 187 2017-04-13T02:34:58Z Imciner2 12 /* Spring 2017 Projects (Videos) */ wikitext text/x-wiki [[Main Page]] ==Spring 2017 Projects ([https://iastate.box.com/cpre488-s2017 Videos])== * A1 - FPGA-Based MIDI Controller * A2 - FPGA-Based Digital Synthesizer * A3 - Advanced USB Turret Controller * A4 - Image-Controlled Pong and Tic-Tac-Toe * A5 - HDMI Image Splitter * B1 - Hardware Accelerated Conway's Game of Life * B2 - Audio Source Localizer * B3 - Networked NES Emulators * B4 - Zedboard SNES Emulator * B5 - Bluetooth Heart Rate Monitoring * B6 - Zedboard Audio using a Bluetooth Speaker * C1 - Smart Home System using Zedboards * C2 - Hardware Acceleration of Convolutional Neural Networks * C3 - Zedboard-Based Oscilloscope * C4 - Secure Communication Between Zedboards * C5 - Remote Camera Security System ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon3/pmodcon3_rm.pdf PmodCON3] || Digilent || 2 || Servo Connector |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon4/pmodcon4_rm.pdf PmodCON4] || Digilent || 3 || RCA to 6-Pin |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodda1/pmodda1_rm.pdf PmodDA1] || Digilent || 1 || Digital to Analog Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodswt/pmodswt_rm.pdf PmodSWT] || Digilent || 2 || 4-Switch Module |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodacl2/pmodacl2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [https://reference.digilentinc.com/_media/pmodamp1/pmodamp1_rm_revb.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbb/pmodbb_rm.pdf PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddip/pmoddip_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddpot/pmoddpot_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodenc/pmodenc_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgps/pmodgps_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgyro/pmodgyro_rm.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodhb3/pmodhb3_rm.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodjstk/pmodjstk_rm.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodkypd/pmodkypd_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodls1/pmodls1_rm.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [https://reference.digilentinc.com/_media/pmod:pmod:pmodMIC_rm.pdf PmodMIC] || Digilent || 2 || Microphone |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodrj45/pmodrj45_rm.pdf PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodrs232/pmodrs232_rm.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodssd/pmodssd_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodstep/pmodstep_rm.pdf PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodtph2/pmodtph2_rm.pdf PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodusbuart/pmodusbuart_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodwifi/pmodwifi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodps2/pmodps2_rm.pdf PmodPS2] || Digilent || 2 || PS2 Module |- | [https://reference.digilentinc.com/_media/pmodreg1/pmodreg1_rm.pdf PmodReg1] || Digilent || 2 || Voltage Regulator |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbtn/pmodbtn_rm.pdf PmodBTN] || Digilent || 1 || 4 User Pushbutton |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} 1ef8ab09bf6be180cfb7ae5ca4918fb87e48fd59 187 186 2017-03-20T14:19:33Z Zambreno 2 /* List of available PMODs and other project components */ wikitext text/x-wiki [[Main Page]] ==Spring 2017 Projects ([https://iastate.box.com/cpre488-s2017 Videos])== * A1 - * A2 - * A3 - * A4 - * A5 - * B1 - * B2 - * B3 - * B4 - * B5 - * B6 - * C1 - * C2 - * C3 - * C4 - * C5 - ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon3/pmodcon3_rm.pdf PmodCON3] || Digilent || 2 || Servo Connector |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon4/pmodcon4_rm.pdf PmodCON4] || Digilent || 3 || RCA to 6-Pin |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodda1/pmodda1_rm.pdf PmodDA1] || Digilent || 1 || Digital to Analog Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodswt/pmodswt_rm.pdf PmodSWT] || Digilent || 2 || 4-Switch Module |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodacl2/pmodacl2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [https://reference.digilentinc.com/_media/pmodamp1/pmodamp1_rm_revb.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbb/pmodbb_rm.pdf PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddip/pmoddip_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddpot/pmoddpot_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodenc/pmodenc_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgps/pmodgps_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgyro/pmodgyro_rm.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodhb3/pmodhb3_rm.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodjstk/pmodjstk_rm.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodkypd/pmodkypd_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodls1/pmodls1_rm.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [https://reference.digilentinc.com/_media/pmod:pmod:pmodMIC_rm.pdf PmodMIC] || Digilent || 2 || Microphone |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodrj45/pmodrj45_rm.pdf PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodrs232/pmodrs232_rm.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodssd/pmodssd_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodstep/pmodstep_rm.pdf PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodtph2/pmodtph2_rm.pdf PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodusbuart/pmodusbuart_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodwifi/pmodwifi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodps2/pmodps2_rm.pdf PmodPS2] || Digilent || 2 || PS2 Module |- | [https://reference.digilentinc.com/_media/pmodreg1/pmodreg1_rm.pdf PmodReg1] || Digilent || 2 || Voltage Regulator |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbtn/pmodbtn_rm.pdf PmodBTN] || Digilent || 1 || 4 User Pushbutton |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} b902c8ff71530bd7b2f48c091ee73d2dab39b127 186 185 2017-03-20T14:12:35Z Zambreno 2 /* List of available PMODs and other project components */ wikitext text/x-wiki [[Main Page]] ==Spring 2017 Projects ([https://iastate.box.com/cpre488-s2017 Videos])== * A1 - * A2 - * A3 - * A4 - * A5 - * B1 - * B2 - * B3 - * B4 - * B5 - * B6 - * C1 - * C2 - * C3 - * C4 - * C5 - ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon3/pmodcon3_rm.pdf PmodCON3] || Digilent || 2 || Servo Connector |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon4/pmodcon4_rm.pdf PmodCON4] || Digilent || 3 || RCA to 6-Pin |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodda1/pmodda1_rm.pdf PmodDA1] || Digilent || 1 || Digital to Analog Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodswt/pmodswt_rm.pdf PmodSWT] || Digilent || 2 || 4-Switch Module |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodacl2/pmodacl2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [https://reference.digilentinc.com/_media/pmodamp1/pmodamp1_rm_revb.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbb/pmodbb_rm.pdf PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddip/pmoddip_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [https://reference.digilentinc.com/_media/reference/pmod/pmoddpot/pmoddpot_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodenc/pmodenc_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgps/pmodgps_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodgyro/pmodgyro_rm.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodhb3/pmodhb3_rm.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodjstk/pmodjstk_rm.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodps2/pmodps2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [https://reference.digilentinc.com/_media/pmodreg1/pmodreg1_rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbtn/pmodbtn_rm.pdf PmodBTN] || Digilent || 1 || 4 User Pushbutton |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} 9e4b92758be9cb89c6bac472cb1296fdf9193e1e 185 184 2017-03-20T14:06:42Z Zambreno 2 /* List of available PMODs and other project components */ wikitext text/x-wiki [[Main Page]] ==Spring 2017 Projects ([https://iastate.box.com/cpre488-s2017 Videos])== * A1 - * A2 - * A3 - * A4 - * A5 - * B1 - * B2 - * B3 - * B4 - * B5 - * B6 - * C1 - * C2 - * C3 - * C4 - * C5 - ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon3/pmodcon3_rm.pdf PmodCON3] || Digilent || 2 || Servo Connector |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodcon4/pmodcon4_rm.pdf PmodCON4] || Digilent || 3 || RCA to 6-Pin |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodda1/pmodda1_rm.pdf PmodDA1] || Digilent || 1 || Digital to Analog Converter |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodswt/pmodswt_rm.pdf PmodSWT] || Digilent || 2 || 4-Switch Module |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodacl2/pmodacl2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [https://reference.digilentinc.com/_media/pmodamp1/pmodamp1_rm_revb.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbb/pmodbb_rm.pdf PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodps2/pmodps2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [https://reference.digilentinc.com/_media/pmodreg1/pmodreg1_rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbtn/pmodbtn_rm.pdf PmodBTN] || Digilent || 1 || 4 User Pushbutton |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} 75525a8cfd1b0e7cc37c10df7d417ff3e02bb2d2 184 182 2017-03-20T03:28:39Z Zambreno 2 /* List of available PMODs and other project components */ wikitext text/x-wiki [[Main Page]] ==Spring 2017 Projects ([https://iastate.box.com/cpre488-s2017 Videos])== * A1 - * A2 - * A3 - * A4 - * A5 - * B1 - * B2 - * B3 - * B4 - * B5 - * B6 - * C1 - * C2 - * C3 - * C4 - * C5 - ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodps2/pmodps2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [https://reference.digilentinc.com/_media/pmodreg1/pmodreg1_rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [https://reference.digilentinc.com/_media/reference/pmod/pmodbtn/pmodbtn_rm.pdf PmodBTN] || Digilent || 1 || 4 User Pushbutton |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} 55a51db88f54fea528faf1ebc19e38c4ba488f9d 182 172 2017-03-07T19:03:03Z Zambreno 2 wikitext text/x-wiki [[Main Page]] ==Spring 2017 Projects ([https://iastate.box.com/cpre488-s2017 Videos])== * A1 - * A2 - * A3 - * A4 - * A5 - * B1 - * B2 - * B3 - * B4 - * B5 - * B6 - * C1 - * C2 - * C3 - * C4 - * C5 - ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} 8a886b9990568af52071bd1b9200cc85281f18b5 172 171 2015-12-21T15:01:48Z Zambreno 2 /* Fall 2015 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects ([https://iastate.box.com/cpre488-f2015 Videos])== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} 171 170 2015-12-21T15:01:10Z Zambreno 2 /* List of available PMODs and other project components */ wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 DS18B20] || Dallas Semiconductor|| 1 || Waterproof Temperature Sensor |} 170 169 2015-12-21T14:59:16Z Zambreno 2 /* List of available PMODs */ wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs and other project components== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 SEN-11050] || SparkFun || 1 || Waterproof Temperature Sensor |} 169 168 2015-12-21T14:58:53Z Zambreno 2 /* List of available PMODs */ wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- | [https://www.sparkfun.com/products/9376 SEN-09376] || SparkFun || 1 || Force Sensitive Resistor (Square) |- | [https://www.sparkfun.com/products/11050 SEN-11050 || SparkFun || 1 || Waterproof Temperature Sensor |} 168 167 2015-11-17T16:45:30Z Zambreno 2 /* Fall 2015 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - Software Defined FM Radio * B3 - Smart Coffee Maker with PID control * B4 - Sign Language Translator using Gesture Recognition * B5 - Hardware Color Filter for Computer Vision Applications * B6 - Electric Guitar Auto-Tuner ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 167 166 2015-11-17T16:39:19Z Zambreno 2 /* Fall 2015 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== * A1 - Stable quad flight using IR tracking * A2 - WiFi video streaming and missile launcher control * A3 - RFID lap counter * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - Hardware Acceleration for Roundness Detection (HARD) * B2 - * B3 - * B4 - * B5 - * B6 - ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 166 165 2015-11-10T15:57:58Z Seiberta 19 /* Fall 2015 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== * A1 - * A2 - WiFi module streaming * A3 - * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - * B2 - * B3 - * B4 - * B5 - * B6 - ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 165 164 2015-11-10T04:28:38Z Nmont 18 /* Fall 2015 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== * A1 - * A2 - * A3 - * A4 - BlockBox: a multifactor personal security box that detects intruders and alerts the owner based on a PING sensor, camera, and keypad. * B1 - * B2 - * B3 - * B4 - * B5 - * B6 - ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 164 163 2015-11-09T20:06:19Z Imciner2 12 wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== * A1 - * A2 - * A3 - * A4 - * B1 - * B2 - * B3 - * B4 - * B5 - * B6 - ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 163 156 2015-11-09T20:05:22Z Imciner2 12 wikitext text/x-wiki [[Main Page]] ==Fall 2015 Projects== ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 156 155 2015-06-26T20:37:10Z Phjones 7 wikitext text/x-wiki [[Main Page]] ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - 2-way audio transmission * A2 - Hand gesture recognition for control of a Nerf cannon system * B1 - High performance LED matrix controller * B2 - Camera-based robot navigation * B3 - Webserver control of a Camera/Turret system ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 155 154 2015-03-27T21:56:24Z Zambreno 2 wikitext text/x-wiki [[Main Page]] ==Spring 2015 Projects ([https://iastate.box.com/cpre488-s2015 Videos])== * A1 - * A2 - * B1 - * B2 - * B3 - ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 154 153 2014-12-19T23:51:00Z Zambreno 2 /* Fall 2014 Projects (Videos) */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects ([https://iastate.box.com/cpre488-f2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 153 152 2014-12-19T23:50:30Z Zambreno 2 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== * A1 - Shadow-based Object Detection: Use K-means clustering algorithm to track multiple objects * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B1 - Ambient Backlight: Extend colors from the edge of a screen and display on a wall * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B3 - PET 2002: A Commodore PET compatible computer in an FPGA * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 152 151 2014-12-05T20:13:21Z Cmilius 16 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone recording multiple tracks and looping their playback on top of one another. * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 151 149 2014-12-05T20:12:21Z Cmilius 16 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * A4 - Audio-loop DJ station: Capture audio-in with a microphone, record multiple audio tracks and loop their playback on top of one another. * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 149 148 2014-11-11T15:21:25Z Rlarsen 14 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * A2 - Bluetooth Bot: A robot using bluetooth to communicate between two boards, such that controls can be on a second board. * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 148 147 2014-11-07T09:19:08Z Jrigdon 13 Added B4 project wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B4 - Expanded NES Emulator: 2- Player Wii Remote Control, "GUI" home screen, audio implementation, SD card save states. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 147 146 2014-11-06T18:25:37Z Imciner2 12 wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * B2 - SNES Emulator: Multiple SNES controller support, Game audio playback, Game save-state to SD card, Game selection menu * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 146 145 2014-11-06T17:23:09Z Jschulz 11 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * A3 - Audio Player with Spectrum Analysis: Play audio, display live frequency spectrum analysis, menu system to choose audio files. * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 145 144 2014-11-05T23:41:29Z Mpvitale 10 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector, have controller to choose song * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 144 143 2014-11-05T23:41:05Z Mpvitale 10 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * B5 - Karaoke Machine: Play a song out of audio-out, have someone sing into a microphone into audio-in, display lyrics on projector * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 143 142 2014-11-05T23:38:49Z Mpvitale 10 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * B5 - Karaoke Machine * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 142 141 2014-11-05T23:38:33Z Mpvitale 10 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * * * B5 - Karaoke Machine ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 141 140 2014-11-05T23:38:24Z Mpvitale 10 /* Fall 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * * * B5 - Karaoke Machone ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 140 122 2014-11-05T23:30:02Z Zambreno 2 wikitext text/x-wiki [[Main Page]] ==Fall 2014 Projects== * * * ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 122 120 2014-08-19T17:06:45Z Zambreno 2 wikitext text/x-wiki [[Main Page]] ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 120 108 2014-07-31T20:12:15Z Zambreno 2 /* Spring 2014 Projects */ wikitext text/x-wiki [[Main Page]] ==Spring 2014 Projects ([https://iastate.box.com/cpre488-s2014 Videos])== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 108 107 2014-04-11T16:59:32Z Tborglum 8 wikitext text/x-wiki [[Main Page]] ==Spring 2014 Projects== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 107 105 2014-04-11T16:56:26Z Tborglum 8 wikitext text/x-wiki ==Spring 2014 Projects== *A1 - Light Preserver: use a microphone that triggers PING sensor on specific sounds; the PING targets the light stopper in Coover 2041 to prevent lights from turning off *A2 - MP-0 Extensions: support 2 players for NES, support audio, add a menu screen, multiple ROMs, and reset ability, and add a GameBoy emulator *A3 - Mouse Control Through Camera: use the camera as a "mouse" to the computer where gestures represent different commands *A4 - Audio Processing: pass audio through the ZedBoard hardware (possibly with modification) and use software pass-through for recording *A5 - PING Sensor Gesture Recognition: use PING sensor with Ubuntu on ZedBoard to recognize gestures that control a media player application *A6 - Multiplayer Battle Station: extend MP-0 and add control through an Android phone over bluetooth connection; missile launcher targets loser *A7 - Temperature Controlled Fan: has user interface to set a temperature, a temperature sensor connected using SPI, and motor control through I2C based on temperature. *B2 - Mobile Turret: use the robot kit with the USB missile launcher and ZedBoard to create a battery-powered turret with path and object detection. *B4 - Hollywood Camera: add hardware manipulation to the image stream of the camera; e.g. green screen, creating grid lines, color shifting/isolating/enhancing, cartoonify, etc. *B5 - Gesture Control Missile Launcher: use a GUI to represent targeting information, increase accuracy, and add gesture controls *B6 - Remote Control Missile Turret: use an Android app to control the turret and send images over the connection *B7 - Oscilloscope: use an ADC to plot signals over time in a GUI sent over VGA or USB *B8 - Battery Load Balancer: use current, temperature, and voltage sensing to get precise battery state information and create a coprocessor to estimate charge ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 105 2014-04-11T16:17:22Z Tborglum 8 New page: ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated ||... wikitext text/x-wiki ==List of available PMODs== {| border="1" |- | Name || Manufacturer || Quantity || Description |- | [http://datasheets.maximintegrated.com/en/ds/DS1086L.pdf DS1086L] || Maxim Integrated || 2 || Oscillator |- | [http://datasheets.maximintegrated.com/en/ds/DS3231M.pdf DS3231M] || Maxim Integrated || 2 || Real-time clock |- | [http://datasheets.maximintegrated.com/en/ds/MAX3222-MAX3241.pdf MAX3232] || Maxim Integrated || 2 || RS232 Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX4822-MAX4825.pdf MAX4824] || Maxim Integrated || 2 || 8-Channel Relay Driver |- | [http://datasheets.maximintegrated.com/en/ds/MAX5214-MAX5216.pdf MAX5216] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX5487-MAX5489.pdf MAX5487] || Maxim Integrated || 2 || Digital Potentiometer |- | [http://datasheets.maximintegrated.com/en/ds/MAX5823-MAX5825.pdf MAX5825] || Maxim Integrated || 2 || 8-Channel ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX7304.pdf MAX7304] || Maxim Integrated || 2 || 16-Port IO |- | [http://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf MAX9611] || Maxim Integrated || 2 || Current Sensor with 12-Bit ADC and OpAmp/Comparator |- | [http://datasheets.maximintegrated.com/en/ds/MAX11205.pdf MAX11205] || Maxim Integrated || 2 || 16-Bit ADC |- | [http://datasheets.maximintegrated.com/en/ds/MAX14840E-MAX14841E.pdf MAX14840E] || Maxim Integrated || 2 || 40 Mbps RS-485 Half-Duplex Transceiver |- | [http://datasheets.maximintegrated.com/en/ds/MAX14850.pdf MAX14850] || Maxim Integrated || 2 || SPI Isolator |- | [http://datasheets.maximintegrated.com/en/ds/MAX31722-MAX31723.pdf MAX31723] || Maxim Integrated || 2 || Temperature Sensor |- | [http://datasheets.maximintegrated.com/en/ds/MAX31855.pdf MAX31855] || Maxim Integrated || 2 || Thermocouple to Digital Converter |- | [http://datasheets.maximintegrated.com/en/ds/MAX44000.pdf MAX44000] || Maxim Integrated || 2 || Proximity Sensor |- | [http://digilentinc.com/Data/Products/PMOD-CON3/Pmod%20Con3_rm.pdf CON3] || Digilent || 2 || Servo Connector |- | [http://www.digilentinc.com/Data/Products/PMOD-CON4/Pmod%20Con%204_rm.pdf CON4] || Digilent || 3 || RCA to 6-Pin |- | [http://www.digilentinc.com/Data/Products/PMOD-DA1/Pmod%20DA1_rm.pdf DA1 Module] || Digilent || 1 || Digital to Analog Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SWITCH/Pmod%20SWT_rm.pdf Digilent Switch Module] || Digilent || 2 || 4-Switch Module |- | [https://digilentinc.com/Data/Products/PMOD-ACL2/PmodACL2_rm.pdf PmodACL2] || Digilent || 2 || 3-Axis Digital Accelerometer |- | [http://www.digilentinc.com/Data/Products/PMOD-AMP1/PmodAMP1_rm_RevB.pdf PmodAMP1] || Digilent || 1 || Speaker/Headphone Amplifier |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,471&Prod=PMOD-BB PmodBB] || Digilent || 1 || Wirewrap/Breadboard |- | [http://www.digilentinc.com/Data/Products/PMOD-DIP/PmodDIP_rm.pdf PmodDIP] || Digilent || 2 || Dual Inline Package |- | [http://digilentinc.com/Data/Products/PMOD-DPOT/PmodDPOT_rm.pdf PmodDPOT] || Digilent || 2 || Digital Potentiometer |- | [http://www.digilentinc.com/Data/Products/PMOD-ENC/PmodENC_rm.pdf PmodENC] || Digilent || 2 || Rotary Encoder |- | [http://www.digilentinc.com/Data/Products/PMOD-GPS/PmodGPS_rm.pdf PmodGPS] || Digilent || 2 || GPS Receiver |- | [https://digilentinc.com/Data/Products/PMOD-GYRO/PmodGYRO_rm_RevA.pdf PmodGYRO] || Digilent || 1 || 3-Axis Digital Gyroscope |- | [http://www.digilentinc.com/Data/Products/PMOD-HB3/PmodHB3_rm_RevD.pdf PmodHB3] || Digilent || 1 || 2A H-Bridge |- | [https://digilentinc.com/Data/Products/XUPV2P-COVERS/PmodJSTK_rm_RevC.pdf PmodJSTK] || Digilent || 2 || Joystick |- | [http://digilentinc.com/Data/Products/PMODKYPD/PmodKYPD_rm.pdf PmodKYPD] || Digilent || 2 || Keypad |- | [http://digilentinc.com/Data/Products/PMOD-LS1/PmodLS1_rm_RevA.pdf PmodLS1] || Digilent || 2 || Infrared Light Detector |- | [http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMOD-MIC PmodMIC] || Digilent || 2 || Microphone |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,477&Prod=PMOD-RJ45 PmodRJ45] || Digilent || 1 || RJ45 to FPGA Connector Pair |- | [https://digilentinc.com/Data/Products/PMOD-RS232/PmodRS232_rm_Rev%20B.pdf PmodRS232] || Digilent || 1 || RS232 Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-SSD/Pmod%20SSD_rm.pdf PmodSSD] || Digilent || 2 || Seven-Segment Display |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,1158&Prod=PMOD-STEP PmodSTEP] || Digilent || 2 || Stepper Motor Controller |- | [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,515&Prod=PMOD-TPH2 PmodTPH2] || Digilent || 2 || 12-Pin Test Point Header |- | [http://www.digilentinc.com/Data/Products/PMOD-USB-UART/PmodUSBUART_rm.pdf PmodUSBUART] || Digilent || 2 || USB to UART Converter |- | [http://www.digilentinc.com/Data/Products/PMOD-WIFI/PmodWiFi_rm.pdf PmodWiFi] || Digilent || 1 || WiFi Radio Transceiver |- | [http://digilentinc.com/Data/Products/PMOD-PS2/Pmod%20PS2_rm.pdf PS2 Module] || Digilent || 2 || PS2 Module |- | [http://www.digilentinc.com/Data/Products/PMOD-REG1/PMod%20REG1_%20rm.pdf Regulator1] || Digilent || 2 || Voltage Regulator |- | [http://www.optekinc.com/datasheets/opb703-705_70a-70d-b.pdf OPB704WZ] || OpTek || 2 || Reflective Object Sensor |- | [http://www.parallax.com/product/28015 PING] || Parallax || 4 || Ultrasonic Distance Sensor (from Cpr E 288) |- |} 0 5 195 193 2017-10-14T02:51:53Z Jiztom 25 Blanked the page wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 193 191 2017-10-13T21:44:14Z Jiztom 25 wikitext text/x-wiki This is a WiKi for those who would like to have remote access to Zedboard. ==Introduction== This manual will give step by step instruction on how to access the zedboard for download over the network with all requirements and possible solutions to common issues. ==Requirements== #''Vivado 2016.2 ''(version specific) installed in the current system you are working on. #System is within the campus network(IASTATE,ISUCARDINAL or eduroam) or using vpn when accessing from outside the network. #.sh script(updated file will be posted in blackboard with this instruction) which mentions the location of the installed vivado 2016.2 on the campus server. #An ssh program to remotely access any remote server(eg. PuTTy, ssh -from terminal). ==Available tools== These are the following available tools on campus # Three servers connected to zync Zedboards. Server access names are: #* xilinx-6.ece.iastate.edu #* xilinx-7.ece.iastate.edu #* xilinx-8.ece.iastate.edu #Vivado 2016.2 installed in the redhat system. To be acces by running the setup.sh as source in Linux. The hardware tools and servers are located in the following address on campus. '''RCL,310, Durham Center''' You can visit the lab incase you need to visually see the output like led blinking or so. ==Instructions== #Open '''Vivado 2016.2''' in your system and work on the project normally. #Once you have generated the bitstream and need to upload the code onto the FPGA (Zync Zedboard to be specific). Note: please check if anyone else is running the same FPGA board before downloading the bitstream. #Choose a server from the list in available tools. Remotely access the server using the ssh protocol. #Go to the directory holding the setup.sh and use the command following. #; $ source setup.sh #:This will set the destination of where the vivado and other tools are installed in the server. #Now run the hw_server as follows. #:'''$ hw_server -s TCP:xilinx-x.ece.iastate.edu:3121''' #:This will run the hardware server on the xilinx server and open port 3121 (also by default). x = 6,7,8 # Now in Vivado in your system open ''Hardware manager'' and select ''Open new Target'' in ''Open Target'', instead of auto connect. #In the following popup dialog box, click next. #In the hardware server setting dialog box, select ''remote server'' in the connect to dropdown list. Fill the remote server host name as the server address on which the hw_server is running.Also fill the port no as 3121 in the port text box. Then click next. #This will connect to the hardware server and show the available devices.Each of the server will be connected to a single FPGA board only. #Select the target and then download the bitstream on to the FPGA. # After the required work is done close the hw_server using Ctrl + C and log out of the server. ==Common Issues== The most common issue that can occur in the process is as follows: #The remote connection says port not opened or no host exists. #:This is due to either few of these reason #*Running wrong version of Vivado either on the remote server or user system. #*Port blocked by Firewall in the network #*hw_server not invoked properly ==Precaution== While handling the Zedboard in the lab the following precautions should be as follows. #Read the Zync Zedboard hardware manual and learn how the jumpers work, #Before running the hw_server in the server please check if anyone else is running the hw_server or ping a request in the class group. # Make sure to shut down (using Ctrl + C) the hw_server after our work with the FPGA is complete. Note: The zedboard or servers are not to be touched or modified. Only the jumper pins and the buttons found on the Zedboard. bb767ef3385dcba809f6b31c2061e2fb753dd93a 191 2017-10-13T21:33:47Z Jiztom 25 Created page with "This is a WiKi for those who would like to have remote access ==Introduction== This manual will give step by step instruction on how to access the zedboard for download over..." wikitext text/x-wiki This is a WiKi for those who would like to have remote access ==Introduction== This manual will give step by step instruction on how to access the zedboard for download over the network with all requirements and possible solutions to common issues. ==Requirements== #''Vivado 2016.2 ''(version specific) installed in the current system you are working on. #System is within the campus network(IASTATE,ISUCARDINAL or eduroam) or using vpn when accessing from outside the network. #.sh script(updated file will be posted in blackboard with this instruction) which mentions the location of the installed vivado 2016.2 on the campus server. #An ssh program to remotely access any remote server(eg. PuTTy, ssh -from terminal). ==Available tools== These are the following available tools on campus # Three servers connected to zync Zedboards. Server access names are: #* xilinx-6.ece.iastate.edu #* xilinx-7.ece.iastate.edu #* xilinx-8.ece.iastate.edu #Vivado 2016.2 installed in the redhat system. To be acces by running the setup.sh as source in Linux. The hardware tools and servers are located in the following address on campus. '''RCL,310, Durham Center''' You can visit the lab incase you need to visually see the output like led blinking or so. ==Instructions== #Open '''Vivado 2016.2''' in your system and work on the project normally. #Once you have generated the bitstream and need to upload the code onto the FPGA (Zync Zedboard to be specific). Note: please check if anyone else is running the same FPGA board before downloading the bitstream. #Choose a server from the list in available tools. Remotely access the server using the ssh protocol. #Go to the directory holding the setup.sh and use the command following. #; $ source setup.sh #:This will set the destination of where the vivado and other tools are installed in the server. #Now run the hw_server as follows. #:'''$ hw_server -s TCP:xilinx-x.ece.iastate.edu:3121''' #:This will run the hardware server on the xilinx server and open port 3121 (also by default). x = 6,7,8 # Now in Vivado in your system open ''Hardware manager'' and select ''Open new Target'' in ''Open Target'', instead of auto connect. #In the following popup dialog box, click next. #In the hardware server setting dialog box, select ''remote server'' in the connect to dropdown list. Fill the remote server host name as the server address on which the hw_server is running.Also fill the port no as 3121 in the port text box. Then click next. #This will connect to the hardware server and show the available devices.Each of the server will be connected to a single FPGA board only. #Select the target and then download the bitstream on to the FPGA. # After the required work is done close the hw_server using Ctrl + C and log out of the server. ==Common Issues== The most common issue that can occur in the process is as follows: #The remote connection says port not opened or no host exists. #:This is due to either few of these reason #*Running wrong version of Vivado either on the remote server or user system. #*Port blocked by Firewall in the network #*hw_server not invoked properly ==Precaution== While handling the Zedboard in the lab the following precautions should be as follows. #Read the Zync Zedboard hardware manual and learn how the jumpers work, #Before running the hw_server in the server please check if anyone else is running the hw_server or ping a request in the class group. # Make sure to shut down (using Ctrl + C) the hw_server after our work with the FPGA is complete. Note: The zedboard or servers are not to be touched or modified. Only the jumper pins and the buttons found on the Zedboard. b8cc8f75ef369425eb6cbc7a163e22daeaf4eacb 6 6 217 2021-02-15T17:08:33Z Phjones 7 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 7 218 2021-02-15T17:09:04Z Phjones 7 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 2 27 2014-02-05T00:18:46Z Dnhushak 3 wikitext text/x-wiki 6 8 222 2021-02-15T18:53:13Z Phjones 7 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 9 223 2021-02-15T18:53:40Z Phjones 7 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709